Analog Devices ADSP-219 Series Hardware Reference Manual Download

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ADSP-2192 Peripheral Device Control Registers

B-68 ADSP-219x/2192 DSP Hardware Reference

SERR# Enable

If any function enables

SERR

driver, then

SERR

may be asserted

Fast Back-to-back
Enable

No function generates fast back-to-back
transactions

Status Register
Bits

Capabilities List

Read-only

66 MHz Capable

Read-only

Reserved

Read-only

Fast Back-to-back
Capable

Read-only.

Master Data Parity
Error

Separate for each function, no interac-
tion

DEVSEL Timing

10-9

Read-only

Signaled Target Abort

Separate for each function, no interac-
tion

Received Target
Abort

Separate for each function, no interac-
tion

Received Master
Abort

Separate for each function, no interac-
tion

Signaled System Error

Separate for each function, set if

SERR

enabled and

SERR

asserted

Detected Parity Error

Separate for each function, but set in all
functions simultaneously

Table B-31. Configuration Space Register Interactions Between Functions
(Continued)

Name

Comments

Summary of Contents for ADSP-219 Series

Page 1: ...quencer Registers on page A 19 Data Address Generator Registers on page A 26 Peripheral Registers on page B 2 When writing DSP programs it is often necessary to set clear or test bits in the DSP s reg...

Page 2: ...grams may clear write zero to the register s reserved bits only Peripheral Registers There are three groups of registers for the ADSP 2192 ADSP 2192 DSP Core Registers on page A 1 ADSP 2192 System Con...

Page 3: ...The ADSP 2192 can respond to up to fourteen interrupts at any given time A list of these interrupts can be found in the table Interrupt Vectors for an ADSP 2192 DSP Core on page 6 14 The AC 97 codec p...

Page 4: ...may be pending at any one time The first write completes with zero PDC wait states A second write launched immediately after the first incurs PDC wait states equivalent to a few AC 97 BITCLKs A third...

Page 5: ...P0 immediately follows with a read to an AC 97 codec register DSP core P0 will be unable to compute DMA or interrupt for 87 89 s DSP core P1 can compute with data in its own memory but cannot communi...

Page 6: ...Register Function 00 B0 Base Register0 01 B1 Base Register1 02 B2 Base Register2 03 B3 Base Register3 04 B4 Base Register4 05 B5 Base Register5 06 B6 Base Register6 07 B7 Base Register7 08 0B Reserved...

Page 7: ...er 31 TCOUNT Timer Counter Register 32 TSCALE Timer Scaling Register 33 TSCALECNT Timer Scale Count Register 34 FLAGS Flags Register 35 3F Reserved 40 43 Reserved 44 MASTADDR DMA Address DSP Master DM...

Page 8: ...1 TX1NXTADDR DMA Next Address FIFO1 Transmit 52 TX1CNT DMA Count FIFO1 Transmit 53 TX1CURCNT DMA Current Count FIFO1 Transmit 54 RX1ADDR DMA Address FIFO1 Receive 55 RX1NXTADDR DMA Next Address FIFO1...

Page 9: ...SRCTL1 registers in each DSP core 64 CNT2 Cycle Counter 2 Register 65 CNT3 Cycle Counter 3 Register MSB 66 FF Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FLOW EMPTY FULL LOOP SDEN FIP2 FIP1 FIP0 SS...

Page 10: ...ers include Rx0NXTADDR Rx1NXTADDR Tx0NXTADDR Tx1NXTADDR and MASTNXTADDR for each DSP core Each register is a 16 bit register con taining a 16 bit word xxxCNT DMA Count Register This group of registers...

Page 11: ...value Table B 2 Register Group Descriptions Page Addresses Descriptions Access permitted by Refer to 0x00 0x00 0x0F ADSP 2192 Chip Control Registers DSP PCI USB page B 13 0x10 0x1F General Purpose I...

Page 12: ...er Space Function 0 DSP1 PCI page B 56 0x0A 0x00 0xFF PCI Configuration Register Space Function 1 DSP1 PCI page B 58 0x0B 0x00 0xFF PCI Configuration Register Space Function 2 DSP1 PCI page B 59 0x0C...

Page 13: ...ace are listed Table B 3 ADSP 2192 Chip Control Registers Register Name Description PCI Address USB Address DSP I O Page DSP I O Address SYSCON Chip Mode Status 0x01 0x00 0x01 0x00 0x00 0x00 PWRCFG0 F...

Page 14: ...r Bit Descriptions Bit Position Bit Name Description 0 RST Soft Chip Reset A write of 1 causes a soft reset to the ADSP 2192 A write of 0 has no effect Always reads 0 Soft Reset affects the DSPs and t...

Page 15: ...may be flushed by three writes in a row to the same location Note This bit resets to zero 3 XON XTAL Force On When 1 causes the XTAL oscillator to run even if all other subsystems are powered down Thi...

Page 16: ...V Regulator Control Disable Disables the on chip 2 5V Regulator controller when the 2 5V IVDD supply is derived from an external regulator e g in USB and Mini PCI applications 0 On Chip 2 5V Regulator...

Page 17: ...nominal 5V 0 if nominal 3 3V 13 PCI 5V PCI 5V level 1 If the PCI ISA CBUS interface is powered from nominal 5V 0 if nominal 3 3V Monitors the level of the PCIVDD pins Read Only 14 Vaux Vaux Present 1...

Page 18: ...RCFG2 Registers Bit Position Bit Name Description 1 0 PWRST 1 0 PCI Function Power State Reports this function s PCI Power Management state from its PMCSR register in PCI Configuration Space Read Only...

Page 19: ...s no effect Always reads 0 15 PME Power Management Event Status Clear 1 A power management event has been detected for this function This is an alias of the PME bit in the Power Management Control Sta...

Page 20: ...is powered down and automatically restarts when either DSP wakes up Note DSP memory cannot be accessed via PCI or USB when the DSP is powered down There is a delay after powering up the DSPs with the...

Page 21: ...a Power Man agement State Change event Read Write 5 AWE DSP Wakeup Enable GPIO Interrupt AC 97 Interrupt When 1 enables this DSP to wake from powerdown upon an event from the indicated source Read Wri...

Page 22: ...3 AINT When 1 an IO interrupt IMASK bit 6 to this DSP is pend ing from the AC 97 port A write of 1 clears this interrupt flag A write of 0 has no effect The AC 97 port should be cleared prior to clear...

Page 23: ...d down The register is controlled by an Adjust bit When the Adjust bit is zero default values for the settings in that segment are used by the PLL These default values are also returned upon a registe...

Page 24: ...DSP I O Page DSP I O Address GPIOCFG GPIO Configuration Direction Control 1 input 0 output 0x010 0x0010 0x00 0x10 GPIOPOL GPIO Polarity Inputs 0 active high 1 active low Outputs 0 CMOS 1 Open Drain 0x...

Page 25: ...F GPIOPUP GPIO Pullup Pull up enable if input 1 enable 0 Hi Z 0x01C 0x001C 0x00 0x1C GPIOPDN GPIO Pulldown Pull down enable if input 1 enable 0 Hi Z 0x01E 0x001E 0x00 0x1E 15 14 13 12 11 10 9 8 7 6 5...

Page 26: ...s register resets to zero GPIO Wakeup Control GPIOWAKECTL Register L This register resets to zero GPIO Status GPIOSTAT Register L This register resets to 0xFF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res...

Page 27: ...s register resets to 0x7F GPIO Pullup GPIOPUP Register L This register resets to 0xFF GPIO Pulldown GPIOPDN Register L This register resets to zero 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved GCTL...

Page 28: ...ster This register is reset by any of the following Power On Reset SYSRST asserted Soft Reset using the PCC RST bit PCI RST asserted when the AC97LCTL DSPR bit is 0 Table B 8 SPROMCTL Control Register...

Page 29: ...ro 6 SEN SEN pin status Default 0 output driving 0 Note This bit resets to zero 7 SCK SCK pin status Default 0 output driving 0 Note This bit resets to zero 12 8 Reserved 13 SDAI SDA pin input enable...

Page 30: ...SP interrupts DSP reads of InBoxes may generate PCI interrupts OutBoxes The outgoing mailboxes OutBox0 and OutBox1 are 16 bits wide They may be read or written by the PCI device or the DSP core DSP wr...

Page 31: ...gister Name Description PCI Address USB Address DSP I O Page DSP I O Address MBXSTAT Mailbox Status 0x021 0x020 0x0021 0x0020 0x00 0x20 MBXCTL Mailbox Control 0x023 0x022 0x0023 0x0022 0x00 0x22 MBX_I...

Page 32: ...ent registers one set per card function The upper 16 bits of each register are reserved and are implemented as read only with 0s These registers are used only in Card Bus systems and have no effect on...

Page 33: ...R CardBus clears GWAKE_E writes 1 PCI PME_Status bit is cleared Power Management event occurs Both GWAKE and PME_Status are set PME may assert Host Interrupt occurs INTRE is set INTA may assert The CS...

Page 34: ...master interrupt mask bit in addition to the other interrupt control regis ters on the ADSP 2192 The INTR_E bit indicates if an interrupt is pending The INTA pin is asserted under the following condi...

Page 35: ...which must be initialized by the DSP from ROM at power up A CISTPL_CONFIG_CB CIS tuple must be provided for each function to point to the function event registers in BAR1 at the appropriate off set Ta...

Page 36: ...t It reads 1 if CB_FPS0 GWAKE has been set by either a wakeup event on AC 97 as enabled by APME or by a wakeup event on GPIOs enabled by GPME A write of a 1 clears this bit This nonvolatile bit is res...

Page 37: ...ster Bit Descriptions Bit Position Bit Name Description 3 0 Reserved 4 GWKM General Wakeup Mask This bit is equivalent to PME_Enable Enables assertion of CSTSCHG in Cardbus mode see above 5 Reserved 6...

Page 38: ...0 INTR 1 CSTSCHG is asserted high when CB_FEM0 INTRM 1 and CB_FEM0 WKUP 1 and CB_FEM0 GWKM 1 and CB_FE0 GWKE 1 This bit is cleared by power on reset and PCI RST It is not affected by SYSRST or Soft Re...

Page 39: ...nt Mask 0x107 0x104 n a 0x01 0x04 CBPRES_STATE0 Function 0 Present State 0x10B 0x108 n a 0x01 0x08 CBEVENT_FORCE0 Function 0 Event Force 0x10F 0x10C n a 0x01 0x0C CBEVENT1 Function 1 Event 0x113 0x110...

Page 40: ...egister Bit Descriptions Bit Position Bit Name Description 3 0 Reserved 4 GWKF Wakeup Force Sets the CB_FE0 GWAKE bit in the Function Event register equivalent to PME_Status Does not affect the state...

Page 41: ...P I O Address AC97LCTL AC 97 Link Control Setup control for AC 97 interface 0x0C1 0x0C0 0x00C1 0x00C0 0x00 0xC0 AC97STAT AC 97 Link Status Setup control for AC 97 interface 0x0C3 0x0C2 0x00C3 0x00C2 0...

Page 42: ...ts in this register reset to zero AC97SIF AC 97 External GPIO Status Register GPIO slot 12 interface register 0x0CB 0x0CA 0x00CB 0x00CA 0x00 0xCA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ARPD AG...

Page 43: ...set to zero AC 97 Input Slot Valid Register AC97SVAL The numbers indicated after the bit name ACSV12 for example indicate the relative slot number Slots are numbered in increasing order 0 first and bi...

Page 44: ...sing order 0 first and bits are numbered in decreasing order MSB first L The bits in the AC97SREQ register reset to zero AC 97 GPIO Status Register AC97SIF L The bits in the AC97SIF register reset to...

Page 45: ...97 Codec Register Space Primary Codec 0 AC97EXT0 Register AC 97 Codec Register Space Secondary Codec 1 AC97EXT1 Register Table B 18 AC 97 External Codec Space 0 Registers Register Name Description PCI...

Page 46: ...registers control bus mastering transactions PCI DMA Control Registers All four PCI DMA control registers listed below share the same bit struc ture and bit descriptions Refer to Setting I O Processo...

Page 47: ...SGVL INTMODE LP EN SGDEN Table B 21 PCI Interrupt Control Registers Register Name Description PCI Address USB Address DSP I O Page DSP I O Address PCI_MSTRCNT0 DMA Transfer Count0 Bus master sample tr...

Page 48: ...ount PCI_MSTRCNT1 Register This 16 bit register contains a count of the number of words to be trans ferred between PCI address space and the DSP internal memory L All bits in this register reset to 0...

Page 49: ...4 3 2 1 0 Word Count 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved LOOP HALT EMPTY FUNCTION 2 0 PACK DIS DSP2 DSP1 Flush FIFO WR RD DMA EN Table B 22 PCI_DMACx Register Bit Descriptions Bit position...

Page 50: ...s of acknowledging one GPIO interrupt by clearing its sticky status and then writing a 1 to PCI_IRQSTAT GPIO while an event occurs on another GPIO it is possible for the ISR to miss the second event s...

Page 51: ...DMA Reserved Table B 23 PCI_IRQSTAT Register Bit Descriptions Bit position Bit name Description 0 Reserved 1 RX0 DMA Rx0 DMA Channel Interrupt Receive Channel 0 Bus Master Transactions Sensitivity Edg...

Page 52: ...to PCI Mailbox 0 Transfer Sensitivity Edge 8 MBox 1 OUT Outgoing Mailbox 1 PCI Interrupt DSP to PCI Mailbox 1 Transfer Sensitivity Edge 9 Reserved 10 Reserved Reserved 11 GPIO General Purpose I O Pin...

Page 53: ...tion Bit name Description 1 0 PCIF 1 0 PCI Functions Configured 00 One PCI Function enabled 01 Two functions 10 Three functions 2 Conf Rdy Configuration Ready When 0 disables PCI accesses to the ADSP...

Page 54: ...registers in the predefined header region as defined in PCI Local Bus Specification Revision 2 2 In addi tion each function contains optional registers to support PCI Bus Power Management Registers t...

Page 55: ...ing bootup Additionally during boot time the DSP will have the possibility of disabling one or more of the functions If only two functions are enabled they will be functions zero and one If only one f...

Page 56: ...arate PME enable and PME status bit Whenever possible the hardware will identify Function 0 wakeup from wakeup and set the appropriate PME status When no determination is possible both PME status bits...

Page 57: ...x0B 0x0A n a 0x09 0x0A PCI_CFG0_SVID Config0 Sub system Vendor ID 0x2D 0x2C n a 0x09 0x2C PCI_CFG0_SDID Config0 Sub system Device ID 0x2F 0x2E n a 0x09 0x2E PCI_CFG0_PWRMT Config0 Power Mgt Capabili t...

Page 58: ...ess to these registers is controlled by the PCI RDY bit in the Chip Mode Status Register Page 0x00 Address 0x00 See ADSP 2192 Chip Control Registers on page B 13 Table B 26 Function 1 Registers Regist...

Page 59: ...ntrolled by the PCI RDY bit in the PCI Interrupt Control Register Page 0x08 Address 0xA2 See General Purpose I O GPIO Control Registers on page B 24 PCI_CFG1_PWRMT Config1 Power Mgt Capabilities Bit 1...

Page 60: ...ystem Vendor ID 0x2D 0x2C n a 0x0B 0x2C PCI_CFG2_SDID Config2 Sub system Device ID 0x2F 0x2E n a 0x0B 0x2E PCI_CFG2_PWRMT Config2 Power Mgt Capabili ties Bit 15 set if Vaux is sensed valid 0x45 0x44 n...

Page 61: ...0x0D Latency Timer 0x0 0x0E Header Type 0x80 Multifunction bit set 0x0F BIST 0x0 Unimplemented 0x13 0x10 Base Address 1 0x08 Register Access for all ADSP 2192 Reg isters Prefetchable Memory 0x17 0x14...

Page 62: ...34 Capabilities Pointer 0x40 Read only 0x3C Interrupt Line 0x0 0x3D Interrupt Pin 0x1 Uses INTA Pin 0x3E Min_Gnt 0x1 Read only 0x3F Max_Lat 0x4 Read only 0x40 Capability ID 0x1 Power Management Capabi...

Page 63: ...s enabled Capabilities List Fast B2B Medium Decode 0x08 Revision ID 0x0 Writable from the DSP during initial ization 0x0B 0x09 Class Code 0x078000 Writable from the DSP during initial ization 0x0C Cac...

Page 64: ...ng initialization 0x33 0x30 Expansion ROM Base Address 0x0 Unimplemented 0x34 Capabilities Pointer 0x40 Read only 0x3C Interrupt Line 0x0 0x3D Interrupt Pin 0x1 Uses INTA Pin 0x3E Min_Gnt 0x1 Read onl...

Page 65: ...s enabled Capabilities List Fast B2B Medium Decode 0x08 Revision ID 0x0 Writable from the DSP during initial ization 0x0B 0x09 Class Code 0x040100 Writable from the DSP during initial ization 0x0C Cac...

Page 66: ...ing initial ization 0x33 0x30 Expansion ROM Base Address 0x0 Unimplemented 0x34 Capabilities Pointer 0x40 Read only 0x3C Interrupt Line 0x0 0x3D Interrupt Pin 0x1 Uses INTA Pin 0x3E Min_Gnt 0x1 Read o...

Page 67: ...ble 0 Enables are separate in each function and go along with the function s base addresses Memory Space Enable 1 Enables are separate in each function and go along with the function s base addresses...

Page 68: ...Master Data Parity Error 8 Separate for each function no interac tion DEVSEL Timing 10 9 Read only Signaled Target Abort 11 Separate for each function no interac tion Received Target Abort 12 Separat...

Page 69: ...Red between func tions any function can access memory Base Address 3 In range signal ORed between func tions any function can access memory Base Address 4 In range signal ORed between func tions any f...

Page 70: ...Clock 3 Read only Reserved 4 Read only Device Specific Ini tialization 5 Read only Aux Current 8 6 Read only by PCI writable by DSP D1 Support 9 Read only D2 Support 10 Read only PME Support 15 11 Rea...

Page 71: ...oint configurations The advan tages to this design are Programmable descriptors and class specific command interpreter An MCU is supported on board which allows you to soft download different configur...

Page 72: ...Buffer Size EP4 0x0C 0x06 0x07 DSP Memory Buffer RD Offset EP4 0x0C 0x08 0x09 DSP Memory Buffer WR Offset EP4 0x0C 0x10 0x13 DSP Memory Buffer Base Addr EP5 0x0C 0x14 0x15 DSP Memory Buffer Size EP5 0...

Page 73: ...0x63 DSP Memory Buffer Base Addr EP10 0x0C 0x64 0x65 DSP Memory Buffer Size EP10 0x0C 0x66 0x67 DSP Memory Buffer RD Offset EP10 0x0C 0x68 0x69 DSP Memory Buffer WR Offset EP10 0x0C 0x70 0x73 DSP Mem...

Page 74: ...P Memory Buffer Base Addr Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X DS BA most significant word 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BA BA BA BA BA BA BA BA BA BA BA...

Page 75: ...r of the memory buffer assigned to this Endpoint Figure B 3 DSP Memory Buffer Size Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SZ SZ SZ SZ SZ SZ SZ SZ SZ SZ SZ SZ SZ SZ SZ SZ Table B 35 DSP Memory...

Page 76: ...ter 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR WR Table B 37 DSP Memory Buffer WR Pointer Offset Register WR 15 0 Memory Buffer WR Offset 0x0XXX Defines general...

Page 77: ...04 0x1005 USB EP5 Description Configures Endpoint 0x1006 0x1007 USB EP5 NAK Counter 0x1008 0x1009 USB EP6 Description Configures Endpoint 0x100A 0x100B USB EP6 NAK Counter 0x100C 0x100D USB EP7 Descri...

Page 78: ...4B USB EP3 Code Download Base Address Starting address for code download on End point 3 0x1060 0x1063 USB EP1 Code Current Write Pointer Offset Current write pointer offset for code down load on Endpo...

Page 79: ...Figure B 6 USB Endpoint Description Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TB LT LT TY TY DR PS PS PS PS PS PS PS PS PS PS Table B 39 USB Endpoint Description Register PS 9 0 Maximum packet s...

Page 80: ...int NAK Counter Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X NE ST NC NC NC NC Table B 40 USB Endpoint NAK Counter Register NC 3 0 NAK counter Number of sequential NAKs that have...

Page 81: ...NK NK NK NK X X X X X TB3 TB2 TB1 ST3 ST2 ST1 FE Table B 41 USB Endpoint Stall Policy Register ST 3 1 A value of 1 means the Endpoint is stalled ST 1 maps to Endpoint 1 ST 2 maps to Endpoint 2 etc TB...

Page 82: ...or DSP code download on Endpoint 1 This register is read write by the MCU only The most significant bit DS bit selects either DSP1 PM address space DS 0 or DSP2 PM address space DS 1 Figure B 9 USB En...

Page 83: ...code download on Endpoint 2 This register is read write by the MCU only The most significant bit DS bit selects either DSP1 PM address space DS 0 or DSP2 PM address space DS 1 Figure B 10 USB Endpoin...

Page 84: ...or DSP code download on Endpoint 3 This register is read write by the MCU only The most significant bit DS bit selects either DSP1 PM address space DS 0 or DSP2 PM address space DS 1 Figure B 11 USB E...

Page 85: ...The sum of this register and the EP1 code download base address regis ter represents the last DSP PM location written This register is read by the MCU only and is cleared to 3FFFF 1 when the Endpoint...

Page 86: ...nt 2 The sum of this register and the EP2 code download base address regis ter represents the last DSP PM location written This register is read by the MCU only and is cleared to 3FFFF 1 when the Endp...

Page 87: ...t 3 The sum of this register and the EP3 code download base address regis ter represents the last DSP PM location written This register is read by the MCU only and is cleared to 3FFFF 1 when the Endpo...

Page 88: ...ister This register is defined as eight bytes long and contains the data sent on the USB from the most recent SETUP transaction This register is read by the MCU only Table B 42 USB SETUP Token Command...

Page 89: ...en Data Register is defined as eight bytes long and contains the data sent on the USB during the data stage This is also where the MCU will write data to be sent in response to a SETUP transaction inv...

Page 90: ...X X X X X X X X X C3 C2 C1 C0 C 3 0 Counter bits IN Transfers The MCU loads the counter with the number of bytes to transfer must be 8 or less since the USB Setup Token Data Register file is 8 bytes m...

Page 91: ...Figure B 16 USB Register I O Address Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Table B 44 USB Register I O Address Register A 15 MCU sets to...

Page 92: ...7 6 5 4 3 2 1 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table B 45 USB Register I O Data Register D 15 0 During READ this register contains the data read from the ADSP 2192 during WRITE...

Page 93: ...051 MCU ISE Current interrupt is for a SETUP token IIN Current interrupt is for an IN token sent with a non zero length data stage IOU Current interrupt is for an OUT token received with a non zero le...

Page 94: ...ister is read by the MCU only Figure B 19 USB Address Endpoint Register 1 5 1 4 1 3 1 2 1 1 10 9 8 7 6 5 4 3 2 1 0 X X X X X EP 3 EP 2 EP 1 EP 0 A 6 A 5 A 4 A 3 A 2 A 1 A 0 Table B 47 USB Address Endp...

Page 95: ...ines ALL ADSP 2192 12 DSP symbolic names ifndef __DEF2192_12_H_ define __DEF2192_12_H_ Begin with a 219x CORE include def219x h System Register bit definitions IRPTL and IMASK registers Bit Positions...

Page 96: ...P Offset 30 FIFO 1 Receive Full define INT_INT13 MK_BMSK_ INT_INT13_P Offset 34 Unused define INT_INT14 MK_BMSK_ INT_INT14_P Offset 38 Unused define INT_AC97FR MK_BMSK_ INT_AC97FR_P Offset 3c AC97 ser...

Page 97: ...Map Chip Control Registers DSP IOPAGE 0x00 define SYSCON 0x00 Chip Mode Status Register define PWRCFG0 0x02 Function 0 Power Management define PWRCFG1 0x04 Function 1 Power Management define PWRCFG2 0...

Page 98: ...olicy for AC 97 Pad Well Bias define SCON_ACVX MK_BMSK_ SCON_ACVX_P AC 97 External Devices Vaux Powered define SCON_XON MK_BMSK_ SCON_XON_P XTAL Force On define SCON_RDIS MK_BMSK_ SCON_RDIS_P Reset Di...

Page 99: ...Selects define PLLC_DPLLM0_P 4 DSP PLL M Divisor Selects define PLLC_DADJ_P 0 DSP PLL Adjust Bit Masks define PLLC_DPLLN1 MK_BMSK_ PLLC_DPLLN1_P DSP PLL N Divisor Selects define PLLC_DPLLN0 MK_BMSK_...

Page 100: ...gister define TX1 0x22 FIFO1 Transmit Data TX register define RX1 0x23 FIFO1 Receive Data RX register define TPERIOD 0x30 Timer Period Register define TCOUNT 0x31 Timer Counter Register define TSCALE...

Page 101: ...x18 GPIO Status Read Pin state Write 0 clear sticky status 1 no effect define GPIOCTL 0x1A GPIO Control w Init r Read Power on state Write Set state of output pins define GPIOPUP 0x1C GPIO Pull up Pul...

Page 102: ...MASK0 0x04 Function 0 Event Mask define CB_PSTATE0 0x08 Function 0 Present State define CB_EVENTFORCE0 0x0C Function 0 Event Force define CB_EVENT1 0x10 Function 1 Event define CB_EVENTMASK1 0x14 Func...

Page 103: ...Count Bits 31 16 define PCI_Tx1BADDRL 0x30 Tx1 DMA Base Address Bits 15 0 define PCI_Tx1BADDRH 0x32 Tx1 DMA Base Address Bits 31 16 define PCI_Tx1CURADDRL 0x34 Tx1 DMA Current Address Bits 15 0 define...

Page 104: ...terrupt Register Status bits for all PCI interrupt sources define PCI_CFGCTL 0x8A PCI Control Includes config register read write control PCI FUNCTION 0 Configuration Space Registers DSP IOPAGE 0x09 N...

Page 105: ...ystem Vendor ID define PCI_SdeviceID2 0x2E Configuration 2 Subsystem Device ID define PCI_PWRMT2 0x44 Configuration 2 Power Mgt Capabilities Bit 15 set if Vaux is sensed valid USB Endpoint DMA Control...

Page 106: ...fine USB_EP9_RD 0x56 Memory Buffer RD Offset EP9 define USB_EP9_WR 0x58 Memory Buffer WR Offset EP9 define USB_EP10_ADDR 0x60 Memory Buffer Base Addr EP10 define USB_EP10_SIZE 0x64 Memory Buffer Size...

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