ADSP-219x/2192 DSP Hardware Reference B-55
ADSP-2192 DSP Peripheral Registers
Each function contains four base address registers that access ADSP-2192
control registers and DSP memory. Base address register (BAR1) accesses
the ADSP-2192 control registers. Accesses to the control registers via
BAR1 use PCI memory accesses. BAR1 requests a memory allocation of
1024 bytes. Access to DSP memory occurs via BAR2 and BAR3. BAR2 is
accesses 24-bit DSP memory (i.e. for DSP program downloading) and
BAR3 accesses 16-bit DSP memory. BAR4 provides I/O space access to
both the control registers and the DSP memory.
The configuration space headers are defined by Function 0 (register infor-
mation shown in
), Function 1 (register
information shown in
), and Function 2 (register
information shown in
Each function is defined by writing to the class code register of that func-
tion during bootup. Additionally, during boot time, the DSP will have the
possibility of disabling one or more of the functions. If only two functions
are enabled, they will be functions zero and one. If only one function is
enabled, it will be function zero.
Interactions Between the Three Functions
Because all functions access and control a single set of resources, potential
conflicts occur in the control specified by the configuration. For each of
the potential conflicts, a resolution is proposed.
and
identify the proposed resolutions (interac-
tions).
covers the registers in the predefined header space and
covers the Power Management registers.
Target accesses to registers and DSP memory can go through any func-
tion. As long as the Memory Space access enable bit is set in that function,
then PCI memory accesses whose address matches the locations pro-
grammed into a function’s BARs 1-3 will be able to read or write any
visible register or memory location within the ADSP-2192. Similarly, if
I/O Space access enable is set, then PCI I/O accesses can be performed via
BAR4.
