Register and Bit #Defines File
B-98 ADSP-219x/2192 DSP Hardware Reference
#define SCON_RDIS_P 2 // Reset Disable
#define SCON_RST_P 0 // Soft Chip Reset
// Bit Masks
#define SCON_PCIRST MK_BMSK_(SCON_PCIRST_P) // PCI Reset
#define SCON_VAUX MK_BMSK_(SCON_VAUX_P ) // Vaux Present
#define SCON_PCI_5V MK_BMSK_(SCON_PCI_5V_P) // PCI 5V level
#define SCON_BUS1 MK_BMSK_(SCON_BUS1_P ) // Bus Mode
#define SCON_BUS0 MK_BMSK_(SCON_BUS0_P ) // Bus Mode
#define SCON_CRST1 MK_BMSK_(SCON_CRST1_P ) // Chip Reset Source
#define SCON_CRST0 MK_BMSK_(SCON_CRST0_P ) // Chip Reset Source
#define SCON_REGD MK_BMSK_(SCON_REGD_P ) // 2.5V Regulator
// Control Disable
#define SCON_VXPD MK_BMSK_(SCON_VXPD_P) // Vaux Policy for AC'97
// Pad Drivers
#define SCON_VXPW MK_BMSK_(SCON_VXPW_P) // Vaux Policy for AC'97
// Pad Well Bias
#define SCON_ACVX MK_BMSK_(SCON_ACVX_P) // AC'97 External Devices
// Vaux Powered
#define SCON_XON MK_BMSK_(SCON_XON_P) // XTAL Force On
#define SCON_RDIS MK_BMSK_(SCON_RDIS_P) // Reset Disable
#define SCON_RST MK_BMSK_(SCON_RST_P) // Soft Chip Reset
//**************************************************
// PWRPx register
//**************************************************
// Bit Positions
#define PWRP_AINT_P 13 // DSP Interrupt Pending from AC'97 Input
#define PWRP_PMINT_P 12 // Power Management Interrupt Pending
#define PWRP_GIEN_P 10 // DSP Interrupt Enable for GPIO Input
#define PWRP_GWE_P 6 // DSP Wake up on GPIO Input Enable
#define PWRP_PMWE_P 4 // Power Management Wake up Enable
#define PWRP_RSTD_P 2 // DSP Soft Reset
#define PWRP_PU_P 1 // DSP Power Up
#define PWRP_PD_P 0 // DSP Power Down
// Bit Masks
#define PWRP_AINT MK_BMSK_(PWRP_AINT_P) // DSP Interrupt Pending
// from AC'97 Input
#define PWRP_PMINT MK_BMSK_(PWRP_PMINT_P) // Power Management
// Interrupt Pending
#define PWRP_GIEN MK_BMSK_(PWRP_GIEN_P) // DSP Interrupt Enable
// for GPIO Input
