ADSP-2192 Peripheral Device Control Registers
B-18 ADSP-219x/2192 DSP Hardware Reference
Power Management Functions
Power management registers share the same bit specifications. Each regis-
ter corresponds to one of the PCI functions:
L
All bits in this register reset to zero.
15
14
13:9
8
7
6
5
4
3
2
1
0
PM
E
SP
ME
Re
se
rv
ed
PM
E EN
R
es
er
ve
d
GP
M
E
AP
ME
Re
se
rv
ed
P
W
RST[
1:0]
Table B-5. Bit Descriptions for PWRCFG0, PWRCFG1, and PWRCFG2
Registers
Bit Position
Bit Name
Description
1:0
PWRST<1:0>
PCI Function Power State.
Reports this function’s PCI Power Management state from its
PMCSR
register in PCI Configuration Space. (Read Only)
4:2
Reserved
5
APME
AC’97 Power Management Event Enable.
1=
Enables setting this function’s
PME
bit upon
an AC’97 interrupt/wake event. (Read/Write)
6
GPME
GPIO Power Management Event Enable.
1=
Enables setting this function’s
PME
bit upon a
GPIO Wakeup event. (Read/Write)
7
Reserved
Reserved
8
PME_EN
Power Management Event Enable.
1=
PME_EN
bit is set in this function’s
PMCSR
register in PCI Configuration space.
13:9
Reserved
