ADSP-219x/2192 DSP Hardware Reference B-5
ADSP-2192 DSP Peripheral Registers
Most AC’97 codec registers may be shadowed, and actual reads should be
rare.
Example
In the worst case, DSP core P1 posts two AC’97 codec register writes just
after the start of a new Frame. DSP core P0 immediately follows with a
read to an AC’97 codec register. DSP core P0 will be unable to compute,
DMA, or interrupt for 87.89 µs. DSP core P1 can compute with data in
its own memory, but cannot communicate with DSP core P0 or access any
PDC bus register for 87.89 µs. The external bus interface can communi-
cate with DSP core P1, but cannot communicate with DSP core P0 or
access any PDC bus register for 87.89 µs. In the state, the entire
ADSP-2192 system is highly constrained.
