ADSP-219x/2192 DSP Hardware Reference B-49
ADSP-2192 DSP Peripheral Registers
DMA Control X - Bus Master Control and Status (PCI_DMACx)
Register
L
All bits in this register reset to 0.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Wo
rd
C
o
u
n
t
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Re
se
rv
ed
L
OOP
HAL
T
EM
PTY
FU
N
C
TI
O
N
<2:
0>
PA
C
K
D
IS
DSP2/D
SP
1
Fl
u
sh
FI
F
O
WR/
R
D
DMA E
N
Table B-22. PCI_DMACx Register Bit Descriptions
Bit
position
Bit name
Description
0
DMA EN
DMA Enable.
1
WR/RD
DMA Write / Read.
2
Flush FIFO
Flush Master FIFO.
3
DSP2/DSP1
Select DSP2 / DSP1.
4
PACK DIS
DMA Packing Disable (DWORD Mode).
7:5
FUNCTION
<2:0>
Function Select (0, 1, and 2).
