ADSP-219x/2192 DSP Hardware Reference B-23
ADSP-2192 DSP Peripheral Registers
DSP PLL Control (PLLCTL) Register
The DSP PLL control register controls the frequencies of the PLL (Phase
Locked Loop) clock generator. Do not write to this register unless the PLL
is powered down.
The register is controlled by an Adjust bit. When the Adjust bit is zero,
default values for the settings in that segment are used by the PLL. These
default values are also returned upon a register read. The default values are
subject to change.
Writing this register to 0 resets the register to its factory defaults.
F
out
=6*F
in
= 98.304 MHz
6*F
in
= 147.456 MHz
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Cse
lR
Cse
lC
Cboos
t
CA
dj
DPLLN
DPLLK
DP
LLM
DselR
DselC
Dboost
DAd
j
