ADSP-219x/2192 DSP Hardware Reference B-19
ADSP-2192 DSP Peripheral Registers
DSP Powerdown (PWRPx) Registers
These two registers share the following bit layout. One register corre-
sponds to each DSP.
L
All bits in this register reset to zero.
14
SPME
Power Management Event (Set).
A write of 1 to this bit sets the
PME
bit for this
function. A write of 0 has no effect. Always
reads 0.
15
PME
Power Management Event (Status/Clear).
1=
A power management event has been detected for this
function. This is an alias of the
PME
bit in the Power
Management Control/Status Register in PCI Configura-
tion Space for this function. A write of 1 to this bit
clears
PME
.
0=
A write of 0 has no effect.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RINT
GI
NT
AINT
PM
IN
T
RIE
N
GI
EN
AIEN
PM
IE
N
RW
E
GW
E
AW
E
PM
WE
FIE
N
RSTD
PU
PD
Table B-5. Bit Descriptions for PWRCFG0, PWRCFG1, and PWRCFG2
Registers (Continued)
Bit Position
Bit Name
Description
