Register and Bit #Defines File
B-102 ADSP-219x/2192 DSP Hardware Reference
// AC'97 Control Registers (DSP IOPAGE=0x00)
#define AC97LCTL 0xC0 // AC'97 Link Control
#define AC97LSTAT 0xC2 // AC'97 Link Status
#define AC97SEN 0xC4 // AC'97 Slot Enable
#define AC97SVAL 0xC6 // AC'97 Input Slot Valid
#define AC97SREQ 0xC8 // AC'97 Slot Request
#define AC97GPIO 0xCA // AC'97 External GPIO Register
// AC'97 External Codec IO Register Spaces
#define AC97CODEC0 0x04 // External Primary Codec 0
// IOPAGE space registers (0x00 - 0x7F)
#define AC97CODEC1 0x05 // External Secondary Codec 1
// IOPAGE space registers (0x00 - 0x7F)
#define AC97CODEC2 0x06 // External Secondary Codec 2
// IOPAGE space registers (0x00 - 0x7F)
// CardBus Function Event Registers (DSP IOPAGE=0x01)
#define CB_EVENT0 0x00 // Function 0 Event
#define CB_EVENTMASK0 0x04 // Function 0 Event Mask
#define CB_PSTATE0 0x08 // Function 0 Present State
#define CB_EVENTFORCE0 0x0C // Function 0 Event Force
#define CB_EVENT1 0x10 // Function 1 Event
#define CB_EVENTMASK1 0x14 // Function 1 Event Mask
#define CB_PSTATE1 0x18 // Function 1 Present State
#define CB_EVENTFORCE1 0x1C // Function 1 Event Force
#define CB_EVENT2 0x20 // Function 2 Event
#define CB_EVENTMASK2 0x24 // Function 2 Event Mask
#define CB_PSTATE2 0x28 // Function 2 Present State
#define CB_EVENTFORCE2 0x2C // Function 2 Event Force
// PCI DMA Address/Count Registers (DSP IOPAGE=0x08)
#define PCI_Rx0BADDRL 0x00 // Rx0 DMA Base Address Bits 15:0
#define PCI_Rx0BADDRH 0x02 // Rx0 DMA Base Address Bits 31:16
#define PCI_Rx0CURADDRL 0x04 // Rx0 DMA Current Address Bits 15:0
#define PCI_Rx0CURADDRH 0x06 // Rx0 DMA Current Address Bits 31:16
#define PCI_Rx0BCNTL 0x08 // Rx0 DMA Base Count Bits 15:0
#define PCI_Rx0BCNTH 0x0A // Rx0 DMA Base Count Bits 31:16
#define PCI_Rx0CURCNTL 0x0C // Rx0 DMA Current Count Bits 15:0
