ADSP-2192 Peripheral Device Control Registers
B-56 ADSP-219x/2192 DSP Hardware Reference
Within the Power Management section of the configuration blocks, there
are a few interactions. The part will stay in the highest power state
between the three functions. Thus if a modem is requested to be powered
down to state
D2,
but Function 0 is set for power state
D0
, the overall chip
will remain in state
D0
. When one or the other of the functions is in a low
power state, they can only respond to configuration accesses, regardless of
the power state of the other functions. Similarly, when a function transi-
tions from
D3hot
to
D0
, that function’s configuration space will be
re-initialized. Each function has a separate PME enable and PME status
bit. Whenever possible, the hardware will identify Function 0 wakeup
from wakeup and set the appropriate PME status. When no determination
is possible, both PME status bits will be set.
PCI Configuration Register Space, Function 0
PCI Configuration Spaces should only be accessed by the DSP, and only
during the boot process. After the PCI interface has been configured, bit 2
of the
PCI_CFGCTL
register (
ConfRdy
) should be set by the DSP. This allows
the PCI interface access to these registers while at the same time denying
the DSP access.
L
Access to these registers is controlled by the PCI RDY bit in the
Chip Mode/Status Register (Page 0x00, Address 0x00).
Table B-25. Function 0 Registers
Register Name
Description
PCI
Address
USB
Address
DSP
I/O
Page
DSP
I/O
Address
PCI_CFG0_VID
Config0 Vendor
ID
0x01-0x00
n/a
0x09
0x00
PCI_CFG0_DID
Config0 Device
ID
0x03-0x02 n/a
0x09
0x02
