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ML365 Virtex-II Pro QDR II SRAM Mem. Board

1-800-255-7778

UG066 (v1.0) June 29, 2004

2.5 V Generation

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1.8 V Generation

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1.5 V Generation

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FPGA Configuration

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Selecting the Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Serial Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Master Serial Mode

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Slave Serial Mode

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SystemAce Configuration (Default Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SelectMap Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
JTAG Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Chapter 3: Electrical Requirements

Power Consumption

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

FPGA Internal Power Budget

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Chapter 4: Signal Integrity Recommendations and Simulations

Termination and Transmission Line Summaries

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Terminations and Transmission Lines for QDR Components

. . . . . . . . . . . . . . . . 34

Data and Clock Signals (D, Q, CQ, CQ, and CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Address and Control Signals (A, R, W, BW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

IBIS Simulations

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Clock Signal Simulations

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Typical, Slow, and Fast Cases for Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Address and Control Signal Simulations

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Typical Case Simulation at All Memory Components . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Chapter 5: Board Layout Guidelines

Decoupling Guidelines

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Providing Additional Ground Pins

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Board Stackup Guidelines

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Appendix 1: Related Documentation

Appendix 2: FPGA Pinout

Appendix 3: Memory Board Schematics and Characterization Results

Schematics

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Characterization Results

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Long-Term Runs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Corners Results Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Product Not Recommended for New Designs

Содержание ML365 Virtex-II Pro QDR II SRAM M

Страница 1: ...R ML365 Virtex II Pro QDR II SRAM 200 MHz Memory Board User Guide UG066 v1 0 June 29 2004 Product Not Recommended for New Designs...

Страница 2: ...own or described herein as is By providing the design code or information as one possible implementation of a feature application or standard Xilinx makes no representation that such implementation is...

Страница 3: ...results of several IBIS simulations Chapter 5 Board Layout Guidelines provides information on decoupling capacitors ground signals and PCB layout Appendix 1 Related Documentation lists data sheet and...

Страница 4: ...olvers Interactive tools that allow you to troubleshoot your design issues http support xilinx com support troubleshoot psolvers htm Tech Tips Latest news design tips and patch information for the Xil...

Страница 5: ...14 FPGA 14 Memories 14 QDR II SRAM U5 Banks 6 and 7 14 QDR II SRAM U11 Banks 2 and 3 14 QDR II SRAM U12 Banks 0 and 1 14 RS232 J5 14 Clocks 14 200 MHz LVPECL Clock Y1 14 250 MHz LVPECL Clock Y2 14 SMA...

Страница 6: ...and Control Signals A R W BW 34 IBIS Simulations 35 Notes on the Simulation Results 35 Data Signal Simulations 36 Data Signals from the FPGA to the Memory HSTL_18_C2 at FPGA 37 Data Signals from the...

Страница 7: ...gure 4 3 Eye Diagram for Data Bit 4 from the FPGA to the QDR II SRAM U11 38 Figure 4 4 Data Signals from the QDR II SRAM U11 at the FPGA Typical Slow Weak and Fast Strong Cases 39 Figure 4 5 Eye Diagr...

Страница 8: ...8 www xilinx com ML365 Virtex II Pro QDR II SRAM Mem Board 1 800 255 7778 UG066 v1 0 June 29 2004 R Product Not Recommended for New Designs...

Страница 9: ...12 JTAG Connector Pins P1 27 Chapter 3 Electrical Requirements Table 3 1 ML365 Power Consumption 29 Table 3 2 XC2VP20FF1152 Estimated Power Consumption 30 Table 3 3 XC2VP20FF1152 Temperature Specific...

Страница 10: ...10 www xilinx com ML365 Virtex II Pro QDR II SRAM Mem Board 1 800 255 7778 UG066 v1 0 June 29 2004 R Product Not Recommended for New Designs...

Страница 11: ...speed QDR II SRAM memory interoperability This document describes the functional blocks within the ML365 It also provides various recommendations and requirements for usage of the board including ele...

Страница 12: ...of the FPGA Features The key features of the ML365 are summarized as follows One Virtex II Pro FPGA XC2VP20FF1152 Three QDR II SRAM Components Samsung K7R323684M or NEC UPD44165364F5 18 MBytes 36 bit...

Страница 13: ...l information on the major blocks Figure 2 1 ML365 Board Block Diagram ug066_c2_01_060804 FPGA Reset PROG Mode DIP SW QDR II SRAM 1M x 36 QDR II SRAM 1M x 36 QDR II SRAM 1M x 36 USER2 Switch USER1 Swi...

Страница 14: ...ace QDR II SRAM U12 Banks 0 and 1 The QDR II SRAM component connected to FPGA I O banks 0 and 1 is a 165 pin 250 MHz Samsung K7R323684M or NEC UPD44165364F5 SRAM This component has a 36 bit wide data...

Страница 15: ...es that connect to the User I Os of the ML365 board GPIO P19 The ML365 board contains 16 General Purpose I Os GPIOs that are accessible through a 2 x 16 100 pin header P19 The odd numbered pins on eac...

Страница 16: ...ue LEDs are installed as status indicators Refer to Table 2 3 Table 2 4 and Table 2 5 Table 2 2 DIP Switch Connections DIP Switch Input FPGA I O Pin DIP1 AF26 M0 DIP2 AE26 M1 DIP3 AE25 M2 Table 2 3 Po...

Страница 17: ...used to apply 5V input power to the board Jumper Settings Table 2 6 lists the jumper settings for the complete PCB Grounded I Os Unused I Os are connected to GND in all FPGA banks This was done to im...

Страница 18: ...e 2 8 lists the LCD write timing parameters Table 2 9 shows the instruction codes for the LCD Figure 2 3 shows the Display Initialization Sequence and Figure 2 7 the LCD panel character set For comple...

Страница 19: ...9 Instruction Code Instruction Code Description Notes 2 and 3 Maximum Execution Time Note 1 RS R W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Clear Display 0 0 0 0 0 0 0 0 0 1 Clears entire display and sets Data...

Страница 20: ...lines F 0 5 x 7 dots BF 1 Internally operating or BF 0 Can accept instruction Cursor or Display Shift 0 0 0 0 0 1 S C R L Moves cursor and shifts display without changing DDR contents 40 s Function S...

Страница 21: ...0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 R E S E T S E Q U E N C E Function Set 8 bit Data Length 2 Line 5 x 7 Dot Format Initialization Flow Chart 15 mS Power On 1 64 uS End of Initializat...

Страница 22: ...linx com ML365 Virtex II Pro QDR II SRAM Mem Board 1 800 255 7778 UG066 v1 0 June 29 2004 Chapter 2 Architecture R Figure 2 4 LCD Panel Character Set ug066_c2_04_060704 Product Not Recommended for New...

Страница 23: ...ermally efficient copper case that is solderable and provides the auxiliary supply for some of the FPGA I Os VCCO 2 5 V Generation The Texas Instruments PT5502N voltage regulator generates the 2 5 V 3...

Страница 24: ...ng modes 1 Not used on QDR II Demonstration Board 2 SystemAce is a Slave Serial configuration mode and is the default for the QDR II Demonstration Board An LED on the Done pin adds a visual aid to det...

Страница 25: ...exist Master Mode FPGA delivers the CCLK download clock Slave Mode FPGA must receive the CCLK clock from the external device The demonstration board can be programmed in both modes using the SelectMap...

Страница 26: ...Figure 2 5 SelectMap Connectors P99 and P111 ug066_c2_05_060804 FPGA CS FPGA RFWR FPGA BUSY FPGA D0 FPGA D1 FPGA D2 FPGA D3 FPGA D4 FPGA D5 FPGA D6 FPGA D7 P99 1 2 3 4 5 6 7 10 8 9 11 12 13 14 15 16 1...

Страница 27: ...the jumper blocks from the P1 pins as specified in Table 2 11 Figure 2 6 shows how to build the JTAG chain and Table 2 12 shows the connections for the JTAG connector P1 Figure 2 6 SystemAce and JTAG...

Страница 28: ...rd 1 800 255 7778 UG066 v1 0 June 29 2004 Chapter 2 Architecture R Figure 2 7 shows the JTAG connector P103 Figure 2 7 JTAG I O Connector P103 ug124_07_0603_04 1 2 3 4 5 6 7 9 8 3 3V GND TCK TDO TDI T...

Страница 29: ...ermination Table 3 1 ML365 Power Consumption Device Quantity Voltage V Current mA Power W Source Total Available Power Power Supply 1 5 6500 32 5 FPGA Power Based on Design FPGA XC2VP20 6 FF1152 1 6 8...

Страница 30: ...page 30 Table 3 5 CLB Logic Power page 31 Table 3 6 Digital Clock Manager Power page 31 Table 3 7 Input Output Power page 31 Table 3 2 XC2VP20FF1152 Estimated Power Consumption Parameter Value Units...

Страница 31: ...Total 12 Table 3 7 Input Output Power Name Frequency MHz I O Standard Type Total Number of Inputs Total Number of Outputs Average IOB Toggle Rate Average Output Enable Rate Average Output Load pF IOB...

Страница 32: ...ML365 Virtex II Pro QDR II SRAM Mem Board www xilinx com 32 UG066 v1 0 June 29 2004 1 800 255 7778 Product Not Recommended for New Designs...

Страница 33: ...Table 4 1 summarizes the terminations for the three QDR II SRAM components for both the FPGA and memory Table 4 1 QDR SRAM Terminations Number Signal Drivers at the FPGA Termination at FPGA Terminati...

Страница 34: ...ual trace The IBIS simulation provided in IBIS Simulations page 35 have been processed using the actual PCB characteristics from the PCB layout tool and the memory and FPGA driver IBIS models Address...

Страница 35: ...Typical Case Slow Weak Case Fast Strong Case Eye Diagram Data signals from the QDR II SRAM to the FPGA U11 Component B Data Q Bit 4 Typical Case Slow Weak Case Fast Strong Case Eye Diagram Clock Signa...

Страница 36: ...nsmission lines Transmit At the memory 100 ohm parallel split termination pulled up to Vdd 1 8 V equivalent to a 50 ohm termination pulled up to Vref 0 9V At the FPGA HSTL_18_C2 drivers Receive At the...

Страница 37: ..._C2 at FPGA The simulations in this subsection test the data signals from the FPGA to the memory Simulations were performed for the following cases typical slow weak and fast strong refer to Figure 4...

Страница 38: ...QDR II SRAM Mem Board 1 800 255 7778 UG066 v1 0 June 29 2004 Chapter 4 Signal Integrity Recommendations and Simulations R Figure 4 3 Eye Diagram for Data Bit 4 from the FPGA to the QDR II SRAM U11 Pr...

Страница 39: ...this subsection test the data signals from the last memory component to the FPGA Simulations were performed for the following cases typical slow weak and fast strong An eye diagram is provided as well...

Страница 40: ...ntegrity Recommendations and Simulations R Eye Diagram for the Component U11 Bit 4 Signal Measured at the FPGA Figure 4 5 shows the eye diagram for the data signals from the FPGA to the last memory co...

Страница 41: ...est conditions for typical slow weak and fast strong cases refer to Figure 4 6 Topology for clock signals 50 ohm transmission lines Clock K At the memory 100 ohm parallel split termination pulled up t...

Страница 42: ...nd Simulations R Typical Slow and Fast Cases for Clock Signals Figure 4 7 shows the simulation waveforms for this case Figure 4 8 shows the simulation waveforms for the Clock K Signal from the FPGA to...

Страница 43: ...QDR II SRAM Mem Board www xilinx com 43 UG066 v1 0 June 29 2004 1 800 255 7778 Clock Signal Simulations R Figure 4 8 Clock CQ Signal from the FPGA to the QDR II SRAM Component U11 Product Not Recommen...

Страница 44: ...signal simulations use the following test conditions for typical slow weak and fast strong cases Topology for data signals 50 ohm Transmission lines At the memory 100 ohm parallel split termination p...

Страница 45: ...RAM Mem Board www xilinx com 45 UG066 v1 0 June 29 2004 1 800 255 7778 Address and Control Signal Simulations R Figure 4 10 Address Control Signals for the QDR II SRAM Component U11 Bit 4 Product Not...

Страница 46: ...46 www xilinx com ML365 Virtex II Pro QDR II SRAM Mem Board 1 800 255 7778 UG066 v1 0 June 29 2004 Chapter 4 Signal Integrity Recommendations and Simulations R Product Not Recommended for New Designs...

Страница 47: ...evices Refer to the Xilinx application note XAPP623 for the implementation methodology A balanced decoupling network is implemented for each bank VCCINT VAUX and VREF Table 5 1 Decoupling Capacitor Re...

Страница 48: ...eramic capacitor X7R C1206 23 33 F ceramic capacitor 10V C7343 9 330 F solid tantalum capacitor 10V C7343 7 VCCINT 1 5V 1 capacitor per pin in a balanced decoupling network 0 01 F ceramic capacitor X7...

Страница 49: ...Trace Spacing Comments 1 Plane GND Gnd 1 Sig 1 Ground plane some memory traces 2 Plane 2 5V 5V Pwr 1 Carve out two power planes on this layer 3 Signal 1 8V 2 5V Sig 2 Some HSTL traces to the memory on...

Страница 50: ...5 Virtex II Pro QDR II SRAM Mem Board 1 800 255 7778 UG066 v1 0 June 29 2004 Chapter 5 Board Layout Guidelines R Figure 5 1 Picture of the Top Layer of the ML365 Revision 1 0b Board Product Not Recomm...

Страница 51: ...QDR II SRAM Mem Board www xilinx com 51 UG066 v1 0 June 29 2004 1 800 255 7778 Board Stackup Guidelines R Figure 5 2 Picture of the Bottom Layer of the ML365 Revision 1 0b Board Product Not Recommend...

Страница 52: ...52 www xilinx com ML365 Virtex II Pro QDR II SRAM Mem Board 1 800 255 7778 UG066 v1 0 June 29 2004 Chapter 5 Board Layout Guidelines R Product Not Recommended for New Designs...

Страница 53: ...n ISR http focus ti com docs prod folders print pt5501 html TPS54810PWP 5V Input 8A Synchronous Buck Converter with Adjustable Output Voltage 1 8V http focus ti com docs prod folders print tps54810 ht...

Страница 54: ...54 www xilinx com ML365 Virtex II Pro QDR II SRAM Mem Board 1 800 255 7778 UG066 v1 0 June 29 2004 Appendix 1 Related Documentation R Product Not Recommended for New Designs...

Страница 55: ...70 10150 32 X1Y111 H26 0 IO_L02N_0 QDR_DREAD_C0 6327 18 X1Y111 G26 0 IO_L02P_0 QDR_DREAD_C1 7905 95 X3Y111 H25 0 IO_L03N_0 QDR_DREAD_C2 5691 71 X3Y111 G25 0 IO_L03P_0 VREF_0 Vref 0 9V 6996 94 X5Y111 J...

Страница 56: ...R_DREAD_C30 13499 9 X29Y111 C22 0 IO_L53_0 No_Pair QDR_DREAD_C31 15061 08 X29Y111 L19 0 IO_L54N_0 QDR_DREAD_C32 2263 39 X29Y111 K19 0 IO_L54P_0 QDR_DREAD_C33 3226 4 X31Y111 G20 0 IO_L55N_0 QDR_DREAD_C...

Страница 57: ...X61Y111 D15 1 IO_L56N_1 QDR_DWRITE_C6 10275 3 X61Y111 D14 1 IO_L56P_1 QDR_DWRITE_C7 10983 43 X61Y111 F15 1 IO_L55N_1 QDR_DWRITE_C8 7549 54 X61Y111 G15 1 IO_L55P_1 QDR_DWRITE_C9 6227 05 X63Y111 K16 1...

Страница 58: ...L08P_1 QDR_DWRITE_C35 16085 61 X85Y111 E9 1 IO_L07N_1 QDR_C_n_C 10718 03 X85Y111 F9 1 IO_L07P_1 QDR_C_C 9223 77 X87Y111 J11 1 IO_L06N_1 QDR_K_n_C 4601 94 X87Y111 K11 1 IO_L06P_1 QDR_K_C 3344 34 X87Y11...

Страница 59: ...N_2 GND 7367 37 X90Y96 L5 2 IO_L36P_2 GND 8143 52 X91Y95 K1 2 IO_L37N_2 QDR_BW_n_C0 12423 45 X91Y94 L1 2 IO_L37P_2 QDR_BW_n_C1 12451 17 X90Y95 N10 2 IO_L38N_2 QDR_BW_n_C2 2788 42 X90Y94 N9 2 IO_L38P_2...

Страница 60: ...DR_DREAD_B16 1247 81 X90Y74 U11 2 IO_L53P_2 QDR_DREAD_B17 1919 47 X90Y73 R7 2 IO_L54N_2 QDR_DREAD_B18 4872 84 X90Y72 R6 2 IO_L54P_2 QDR_DREAD_B19 6425 42 X91Y71 P1 2 IO_L55N_2 QDR_DREAD_B20 11291 77 X...

Страница 61: ..._3 Vref 0 9V 9812 03 X91Y50 Y2 3 IO_L87P_3 QDR_DWRITE_B6 10611 96 X91Y49 V9 3 IO_L86N_3 QDR_DWRITE_B7 3327 27 X91Y48 V10 3 IO_L86P_3 QDR_DWRITE_B8 2405 17 X90Y49 W3 3 IO_L85N_3 QDR_DWRITE_B9 8919 9 X9...

Страница 62: ...RITE_B35 5836 46 X91Y28 AA8 3 IO_L47P_3 4888 88 X90Y29 AB5 3 IO_L46N_3 QDR_SA_B0 7371 9 X90Y28 AB6 3 IO_L46P_3 QDR_SA_B1 6629 5 X91Y27 AC2 3 IO_L45N_3 VREF_3 Vref 0 9V 10601 93 X91Y26 AD2 3 IO_L45P_3...

Страница 63: ...D 15821 97 X91Y6 AL2 3 IO_L06P_3 GND 15583 83 X91Y5 AG7 3 IO_L05N_3 GND 9638 17 X91Y4 AH8 3 IO_L05P_3 DONE 9015 73 X90Y5 AH5 3 IO_L04N_3 GND 9452 34 X90Y4 AH6 3 IO_L04P_3 GND 9308 27 X91Y3 AK3 3 IO_L0...

Страница 64: ...ER2_PB 5289 64 X72Y0 AJ13 4 IO_L44N_4 GND 9198 92 X72Y0 AK13 4 IO_L44P_4 GND 10605 95 X70Y0 AL11 4 IO_L45N_4 GND 10900 17 X70Y0 AM11 4 IO_L45P_4 VREF_4 GND 12224 04 X68Y0 AE15 4 IO_L46N_4 USER2_LED 31...

Страница 65: ...0 AK17 4 IO_L75N_4 GCLK1S OSC_250M_N X46Y0 AL17 4 IO_L75P_4 GCLK0P OSC_250M_P X44Y0 AL18 5 IO_L75N_5 GCLK7S EXTCLK1_N X44Y0 AK18 5 IO_L75P_5 GCLK6P EXTCLK1_P X44Y0 AJ18 5 IO_L74N_5 GCLK5S GND X44Y0 AH...

Страница 66: ...2 5 IO_L44N_5 GND 10795 23 X18Y0 AJ22 5 IO_L44P_5 GND 9429 62 X18Y0 AF21 5 IO_L43N_5 GND 5289 64 X18Y0 AE21 5 IO_L43P_5 MASTER_RESET 3696 3 X12Y0 AK24 5 IO_L39N_5 GND 9736 03 X12Y0 AJ24 5 IO_L39P_5 GN...

Страница 67: ...5N_6 QDR_BW_n_A3 9638 17 X1Y6 AL33 6 IO_L06P_6 QDR_C_n_A 15583 83 X1Y7 AL34 6 IO_L06N_6 QDR_C_A 15821 97 X0Y8 AF31 6 IO_L31P_6 QDR_W_n_A 10021 36 X0Y9 AF32 6 IO_L31N_6 QDR_R_n_A 10624 52 X1Y8 AC25 6 I...

Страница 68: ...29 6 IO_L46P_6 QDR_DWRITE_A16 6629 5 X0Y29 AB30 6 IO_L46N_6 QDR_DWRITE_A15 7371 9 X1Y28 AA27 6 IO_L47P_6 QDR_DWRITE_A14 4888 88 X1Y29 AA28 6 IO_L47N_6 QDR_DWRITE_A13 5836 46 X1Y30 AB31 6 IO_L48P_6 QDR...

Страница 69: ...IO_L87P_6 QDR_SA_A6 10611 96 X1Y51 W33 6 IO_L87N_6 VREF_6 Vref 0 9V 9812 03 X0Y52 V29 6 IO_L88P_6 QDR_SA_A5 5998 02 X0Y53 V30 6 IO_L88N_6 QDR_SA_A4 6547 9 X1Y52 V27 6 IO_L89P_6 QDR_SA_A3 4483 54 X1Y5...

Страница 70: ...4N_7 QDR_DREAD_A15 4872 84 X0Y74 U24 7 IO_L53P_7 QDR_DREAD_A16 1919 47 X0Y75 T24 7 IO_L53N_7 QDR_DREAD_A17 1247 81 X1Y74 P32 7 IO_L52P_7 GND 9339 48 X1Y75 P31 7 IO_L52N_7 VREF_7 Vref 0 9V 8102 88 X0Y7...

Страница 71: ...A34 12451 17 X1Y95 K34 7 IO_L37N_7 QDR_DREAD_A35 12423 45 X0Y96 L30 7 IO_L36P_7 GND 8143 52 X0Y97 L29 7 IO_L36N_7 R_n_int_A 7340 48 X0Y98 L28 7 IO_L35P_7 GND 6793 53 X0Y99 L27 7 IO_L35N_7 GND 5592 79...

Страница 72: ...0 12 J26 PROG_B PROG_B K25 HSWAP_EN HSWAP K26 DXP G27 DXN G8 RSVD K9 VBATT GND K10 TMS JTAG_TMS J9 TCK JTAG_TCK H7 DO FPGA_TDO AE9 CCLK FPGA_CCLK AF9 PWRDWN_B PWRDWN AE10 DONE FPGA_DONE AE25 M2 M2 AF2...

Страница 73: ...AP8 TXPPAD16 AP9 TXNPAD16 AP14 RXNPAD18 AP15 RXPPAD18 AP16 TXPPAD18 AP17 TXNPAD18 AP18 RXNPAD19 AP19 RXPPAD19 AP20 TXPPAD19 AP21 TXNPAD19 AP26 RXNPAD21 AP27 RXPPAD21 AP28 TXPPAD21 AP29 TXNPAD21 Table...

Страница 74: ...74 www xilinx com ML365 Virtex II Pro QDR II SRAM Mem Board 1 800 255 7778 UG066 v1 0 June 29 2004 Appendix 2 FPGA Pinout R Product Not Recommended for New Designs...

Страница 75: ...ix 3 Memory Board Schematics and Characterization Results This section provides schematics for the ML365 Virtex II QDR SRAM Memory Demonstration Board as well as characterization results Schematics Th...

Страница 76: ...onal Decoupling Caps Revision Notes are on Sheet 28 28 12 Rev Notes 1 12 Notes Page 6 5 QDRII SRAM 1 Termination Resistors 8 5 QDRII SRAM 2 Termination Resistors placeholder 10 5 QDRII SRAM 3 Terminat...

Страница 77: ..._CQ _n_A Q DR_CQ _A Q DR_C_A Q DR_C_n_A QDR_K_A QDR_K_n_A GND_SIGNAL 1 8V 0 9V_QDR QDR_BW_n_A 3 0 CONFIG_EE PR O M SYSACE_MPD 7 0 SYSACE_MPA 6 0 SYSACE_MPWE SYSACE_MPOE SYSACE_MPCE SYSACE_TDO TMS TC K...

Страница 78: ...Number R ev D at e Sheet o f D oc 0 M L365 QD R I I SRAM Inter f ace Boar d B 3 28 01 22 04 0 9 0 7 44 CLOCKS Differential Inputs for Test Equip clock PECL out SMT LCC package EG2121CA200 0000M PHPAB...

Страница 79: ...72 POR_TEST 74 MPBRDY 39 MPIRQ 41 MPCE 42 MPA04 45 MPA05 44 MPA06 43 MPD00 66 MPD01 65 MPD02 63 MPD03 62 MPD04 61 MPD05 60 MPD06 59 MPD07 58 MPD08 56 MPD09 53 MPD10 52 MPD11 51 MPD12 50 MPD13 49 MPD1...

Страница 80: ..._DW RITE_A 35 0 Q DR_R_n_A QDR_K _A Q D R_K_n_A QDR_W _n_A QDR_ C Q _A QDR_CQ_n _A 0 9V_QDR 1 8 V GND_S I G N AL QDR_C_A Q DR_C_n_A Q D R _BW _n_A 3 0 0 9V_QDR 1 8 V 1 8V 0 9V_QDR 1 8 V 1 8V 1 8V 1 8V...

Страница 81: ...A_A7 Q D R _SA_A1 1 8V 1 8V 1 8V Q D R _W R IT E_A 35 0 Q D R _SA_A 17 0 1 8V GND_SI G N AL Title Si ze Document Number R ev D at e Sheet o f Doc 5 M L365 QDR II SRAM Inte r f ace Boar d B 6 28 01 22...

Страница 82: ...n_B2 Q D R _BW _n_B3 0 9V_QDR 1 8V GND_SI G N AL Q D R_R_n_B QDR_K_B Q D R _K_n_B QDR_W _n_B QDR_C_B Q D R_C_n_B Q D R _SA_B 17 0 QDR_DW RITE_B 35 0 QDR_ C Q _B QDR_CQ_n_B QDR_DREAD_B 35 0 Q D R _BW _...

Страница 83: ...1 8V Q D R _SA_B 17 0 1 8V GND_SI G N AL Q D R _W R IT E_B 35 0 Title Si ze Document Number R ev D at e Sheet o f Doc 5 M L365 QDR II SRAM Inte r f ace Boar d B 8 28 01 22 04 09 07 46 QDRII SRAM 2 Te...

Страница 84: ..._C Q D R _C Q _n_C 0 9V_QDR 1 8V GND_SI G N AL QDR_R_n_C QDR_K_C Q D R_K_n_C Q D R _W _n_C QDR_C_C QDR_C_n_C QDR_SA_C 1 7 0 QDR_DW RITE_C 35 0 QDR_BW _n_C 3 0 1 8V 1 8V 0 9V_QDR 1 8V 1 8V 0 9V_QDR 1 8...

Страница 85: ...R_SA_C0 1 8V 1 8V 1 8V QDR_W R IT E_C 35 0 1 8V QDR_SA_C 1 7 0 GND_SI G N AL Title Si ze Document Number R ev D at e Sheet o f Doc 5 M L365 QDR II SRAM Inte r f ace Boar d B 10 28 01 22 04 09 07 47 Q...

Страница 86: ...ace Boar d B 11 28 03 15 04 08 49 10 BANK0 QDRII SRAM 3 QDR C DREAD Interface 250MHz DCM driven IN R294 100 R295 100 R504 100 C430 0 1uF R503 100 BANK0 U6A XC2VP20 IO_L01N_0 VRP_0 E29 IO_L01P_0 VRN_0...

Страница 87: ...v D at e Sheet o f Doc 11 M L365 QDR II SRAM Inte r f ace Boar d B 12 28 03 15 04 08 49 10 BANK1 QDRII SRAM 3 QDR C DWRITE Interface 250MHz DCM driven OUT R115 51 BANK1 U6B XC2VP20 IO_L75N_1 GCLK3P H1...

Страница 88: ...11 M L365 QDR II SRAM Inte r f ace Boar d B 13 28 03 15 04 08 49 10 BANK2 QDRII SRAM 3 QDR C SA address Interface QDRII SRAM 2 QDR B DREAD Interface IN BANK2 U6C XC2VP20 IO_L01N_2 VRP_2 D2 IO_L01P_2 V...

Страница 89: ...at e Sheet o f Doc 11 M L365 QDR II SRAM Inte r f ace Boar d B 14 28 03 15 04 08 49 10 BANK3 QDRII SRAM 2 QDR B DWRITE SA Address Interfaces OUT R121 51 R120 51 C433 0 1uF BANK3 U6D XC2VP20 IO_L90N_3...

Страница 90: ...K R153 51 R88 51 SW 7 SW PUSHB U TTO N R139 270 R149 51 R145 51 R136 10K R298 51 R154 51 R538 4 7K R138 10K R150 51 R140 51 R146 51 R299 51 R142 51 G S D Q7 BSS138 R155 51 BANK4 U6E XC2VP20 IO_L01N_4...

Страница 91: ...terfaces Master Reset switch N O R106 10K R275 51 P12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SW 5 SW PUSHB U TTO N R274 51 BANK5 U6F XC2VP20 IO_L75N_5 GCLK7S AL18 IO_L75P_5 GCLK6P AK18 IO_L74N_5...

Страница 92: ...DR II SRAM Inte r f ace Boar d B 17 28 03 15 04 08 49 11 BANK6 QDRII SRAM 1 Memory Interface 36 bit QDR_DWRITE_A 35 0 and QDR_SA_A 17 0 OUT C373 0 1uF R122 51 BANK6 U6G XC2VP20 IO_L01P_6 VRN_6 AJ30 IO...

Страница 93: ...U6H XC2VP20 IO_L90P_7 U32 IO_L90N_7 U31 IO_L89P_7 U28 IO_L89N_7 U27 IO_L88P_7 V33 IO_L88N_7 VREF_7 U33 IO_L87P_7 U30 IO_L87N_7 U29 IO_L86P_7 U26 IO_L86N_7 U25 IO_L85P_7 T32 IO_L85N_7 T31 IO_L60P_7 T30...

Страница 94: ...W16 GND83 W17 GND84 W18 GND85 W19 GND86 W20 GND87 W21 GND88 W34 GND89 Y8 GND90 Y14 GND91 Y15 GND92 Y16 GND93 Y17 GND94 Y18 GND95 Y19 GND96 Y20 GND97 Y21 GND98 Y27 GND99 AA14 GND100 AA15 GND101 AA16 G...

Страница 95: ...RXPPAD19 AP19 AVCCAUXTX19 AN20 VTTXPAD19 AN21 GNDA19 AM20 VTRXPAD19 AN19 AVCCAUXRX19 AN18 TXNPAD21 AP29 TXPPAD21 AP28 RXNPAD21 AP26 RXPPAD21 AP27 AVCCAUXTX21 AN28 VTTXPAD21 AN29 GNDA21 AM27 VTRXPAD21...

Страница 96: ...32 NC7_6 J31 NC7_7 J30 NC7_8 J29 NC7_9 G34 NC7_10 G33 NC7_11 H30 NC7_12 H29 NC2_13 J6 NC2_14 J5 NC2_15 J4 NC2_16 J3 NC2_17 K8 NC2_18 K7 NC2_19 H4 NC2_20 H3 NC3_13 AJ1 NC3_14 AJ2 NC3_15 AF7 NC3_16 AF8...

Страница 97: ...r d B 22 28 01 22 04 0 9 0 7 47 LCD CONNECTOR 1x16 INLINE 025SQ PINS 16 char x 2 line Seiko L167100J000 This LCD requires two rows of 16 pins to support it physically Place the 1X16 SIP headers 31mm a...

Страница 98: ...t e Sheet o f D oc 0 M L365 QD R I I SRAM Inter f ace Boar d B 23 28 01 22 04 0 9 0 7 48 RS232 DRIVER GND1 2 are mounting holes DB9 Female check pin 2 and 3 for RX and TX C13 0 1uF R36 100 C12 0 1 uF...

Страница 99: ...111C Vfwd 3 3V If 10mA may be too high s b 3 3K change to blue Slide switch is for ON OFF 5V input via barrel jack Make layout template and duplicate for each reg LOCAL POWER REGULATION U10 PT5501N IN...

Страница 100: ...ller PM1812 2R2J 2 2uH 380mA 1812 Nominal 0 9V for QDR ref 0 9V for QDR 1206 0 6V to 1 2V ref for FPGA Ceramic X5R 0805 6 3V CD ESRE151M06R C385 10uF R126 4 7K L5 2 5uH R307 4 7K R308 3 48 K 1 R135 1K...

Страница 101: ...0 01uF C137 0 01uF C62 0 01uF C113 0 01uF C133 0 01uF C308 0 047 uF C74 0 01uF C365 0 047 uF C139 0 01uF C30 0 047 uF C325 0 047 uF C202 2 2 uF C80 33uF 1 2 C82 330uF 1 2 C79 0 01uF C128 0 01uF C158...

Страница 102: ...uF C212 2 2uF C271 0 01uF C248 2 2uF P27 H EA DER 1 1 C88 0 01uF C277 2 2uF C109 0 01uF C231 0 01uF C208 2 2uF C195 0 01uF C282 0 047uF C266 0 01uF C192 0 01uF C264 0 01uF C241 33uF 1 2 C225 0 01uF C2...

Страница 103: ...A DONE signal to Bank3 AH8 Added 1K 25 turn trimpot to 0 9V_FPGA vref to give 0 6V to 1 2V adjustment Change TPS54610 1 8V 6A to TPS54810 1 8V 8A power 6 Updated component footprints only no changes t...

Страница 104: ...the optimal value for the memory interface under test At optimal voltage 1 800V it appears that 0 900V was in almost all cases the optimal setting variations of 1 8V required significant adjustments...

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Содержание ML365 Virtex-II Pro QDR II SRAM M

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