Counter/Timer Operation
94 – CIO Chip
VL-486-4 Reference Manual
If a second match occurs while IP is already set, an error condition exists. If the Interrupt ON
Error bit (IOE) is 0, the match is ignored. However, if IOE is 1 after the first IP is cleared, the IP
is automatically set to 1 along with the Interrupt Error (ERR) flag. ERR is automatically cleared
when the corresponding IP is cleared by software.
When a pattern-match is present in the OR-Priority Encoded Vector mode, IP is set to 1. The IP
cannot be cleared until a match is no longer present. If the interrupt vector is allowed to include
status, the vector returned during Interrupt Acknowledge indicates the highest-priority bit
matching its specification at the time of the Acknowledge cycle. Bit 7 is the highest-priority bit
and bit 0 is the lowest-priority bit. The bit initially causing the interrupt may not be the one
indicated by the vector if a higher-priority bit matches before the Acknowledge. Once the
Interrupt Acknowledge cycle is initiated, the vector is frozen until the corresponding Interrupt
Under Service (IUS) is cleared. If an input that causes interrupts changes before the interrupt is
serviced, the 1’s catcher can be used to hold the value. Bits should not be specified with
transition detection, because the match will no longer be valid at the time of the Interrupt
Acknowledge. If no match is present at the time of the Acknowledge, the vector will indicate the
lowest-priority bit (Bit 0).
Because a no-match-to-match transition is not required, the source of the interrupt must be
cleared before IP is cleared or else a second interrupt is generated. No programmer error
detection is performed in this mode and the Interrupt on Error bit should be 0.
One application of the OR-PEV pattern match mode is to use the CIO as a Programmable
Interrupt Controller (PIC).
Counter/Timer Operation
C
OUNTER
/T
IMER
A
RCHITECTURE
The three independent 16-bit counter/timers each consist of a presettable 16-bit down-counter, a
16-bit Time Constant register, a 16-bit Current Counter register, an 8-bit Mode Specification
register, an 8-bit Command and Status register, and the associated control logic that links these
registers.
The flexibility of the counter/timers is enhanced by the provision of up to four lines per
counter/timer (counter input, gate input, trigger input, and counter/timer input) for direct external
control and status. Counter/Timer 1’s external I/O lines are provided by the four most-significant
bits of Port B. Counter/Timer 2’s external I/O lines are provided by the four least-significant bits
of Port B. Counter/Timer 3’s external I/O lines are provided by the four bits of Port C. The
utilization of these lines (Table 4-1) is programmable on a bit-by-bit basis via the Counter/Timer
Mode Specification registers.
When external counter/timer I/O lines are to be used, the associated port lines must be vacant
and programmed in the proper data direction. Lines used for counter/timer I/O have the same
characteristics as simple input lines. They can be specified as inverting or non-inverting, and can
be read and used with the pattern-recognition logic. They can also include the 1’s catcher input.
