Pattern Definition Registers
86 – CIO Chip
VL-486-4 Reference Manual
Table 60: Register Bit Assignments
Bit
Mnemonic
Description
D7
C/SC
Continuous/Single Cycle — If C/SC is set to 1, then each time the down-
counter reaches the count of 1, the time constant value is reloaded (on the
next count) and the countdown sequence is repeated. If C/SC is 0 when the
count of 1 is encountered (and, for square-wave outputs, if the output is 1), the
counter is allowed to count down to 0 and the countdown sequence is
terminated.
D6
EOE
External Output Enable — By programming this bit to be 1, the output of the
counter/timer is provided on the I/O line of the port associated with that
particular counter/timer. This bit should not be set to 1 unless the
corresponding bit is available, (it is not being used as part of an input or output
port). The bit must be programmed to be an output bit in the Data Direction
register of its port.
D5
ECE
External Count Enable — When ECE is set to 1, the counter/timer is put into
the counter mode. The I/O line of the port associated with the counter/timer is
used as an external counter input. On each rising edge of the count input
(when the data path is specified non-inverting), the down-counter is
decremented. The bit must be available and it must be specified to be an
input. (Even if the port bit is programmed as an output bit, the port pin, [if
enabled] is used as the counter/timer input, allowing the CPU to write this
input directly.)
D4
ETE
External Trigger Enable — When ETE is set to 1, the I/O line of the port
associated with the counter/timer is used as a trigger to input the
counter/timer. A rising edge (when the data path is specified non-inverting) on
this line will cause the down-counter to be loaded. To guarantee that the
counter/timer will be triggered on a particular rising edge of the clocking signal
(PCLK/2 or counter input), the trigger rising edge must satisfy a setup time to
the preceding falling edge of the clocking signal. As in the external count input,
the bit of the port must be available for use by the counter/timer, and must be
programmed as an input bit. (Even if the port bit is programmed as an output
bit, the port pin is used as the counter/timer input [if enabled], allowing the
CPU to write this input directly.)
D3
EGE
External Gate Enable — By setting EGE to 1, the I/O line of the port
associated with the counter/timer is used as an external gate input to the
counter/timer. If the external gate input is a 0 (assuming the data path is
programmed non-inverting), the countdown sequence is suspended; forcing it
to a 1 enables the countdown sequence to continue. To guarantee the
enabling or disabling of the counter/timer for a particular rising edge of the
clocking signal (PCLK/2 or counter input), the gate input must satisfy a setup
time to the preceding falling edge of the clocking signal. Like external trigger
input, the bit must be available and it must be programmed to be an input.
(Even if the port bit is programmed as an output bit, the port pin is used as the
counter/timer input if enabled. This allows the CPU to write this input directly.)
D2
REB
Retrigger Enable Bit — If REB is set to 0, triggers (internal or external) which
occur during a countdown sequence are ignored. If REB is 1, each trigger
causes the time constant value to be reloaded and a new countdown will start
on the first half of the square-wave cycle.
D1-D0
DCS1-DCS0
Output Duty Cycle Selects — These two bits select the output duty cycle.
DCS1
DCS0
Output Duty Cycle
0
0
Pulse Output
0
1
One-Shot Output
1
0
Square-Wave Output
1
1
DO NOT USE
