Port Handshake Specification Registers
80 – CIO Chip
VL-486-4 Reference Manual
Table 55: Register Bit Assignments
Bit
Mnemonic
Description
D7
(Read)
IUS
Interrupt Under Service — This status bit is automatically set to 1 if its
corresponding IP is the highest-priority interrupt request pending when an
Interrupt Acknowledge sequence takes place. It can also be set directly by
CPU command. The same and lower priority sources of interrupt are
prohibited from requesting interrupts via the internal and external daisy-chains.
The IUS can be cleared to 0 only by CPU command. This bit is read/write. It is
changed by writing to this register using the coded ICB2-ICB0 bits.
D6
(Read)
IE
Interrupt Enable — This bit enables or disables the port's interrupt logic.
While IE is cleared to 0, the port is unable to request an interrupt or to respond
to an Interrupt Acknowledge. The normal operation of IP or IUS is not affected,
the IP is simply masked off from the rest of the device. A 1 in IUS still affects
the interrupt daisy-chain. If IE is programmed to be 1, the interrupt logic
operates normally. This is bit read/write. It is changed by writing to this register
using the coded ICB2-ICB0 bits.
D5
(Read)
IP
Interrupt Pending — IP is a status bit which, when set to 1, indicates that the
port requires servicing due to a pattern match, a handshake, or an error. It is
set to1 by the port logic (or by the CPU command). If IE is also 1 and no
higher-priority interrupts are under service, then the INT line is pulled Low to
request an interrupt. It is cleared to 0 either automatically or by a CPU
command, depending on port configuration. This is bit read/write. It is changed
by writing to this register using the coded ICB2-ICB0 bits.
D7-D5
(Write)
ICB2-ICB0
Interrupt Command Bits — These three bits control the port IP, IUS, and IE
bits.
ICB2
ICB1
ICB0
Function
0
0
0
Null Code
0
0
1
Clear IP and IUS
0
1
0
Set IUS
0
1
1
Clear IUS
1
0
0
Set IP
1
0
1
Clear IP
1
1
0
Set IE
1
1
1
Clear IE
D4
(Read)
ERR
Interrupt Error — This status bit is automatically set to 1 along with IP when,
for a bit port with pattern match enabled, a second match occurs before a
previous match is acknowledged (IP is still set). If the port Interrupt On Error
(IOE) bit is 0, errors are ignored and this bit is held at 0. This bit can be
cleared only by clearing the corresponding IP. This bit is a read-only bit; writes
to it are ignored.
D3
(Read)
ORE
Output Data Register Empty — ORE is a status bit. It is forced to 1 unless
OR-PEV pattern match mode is specified--in which case, ORE is forced to 0.
This bit is a read-only bit; writes to it are ignored. RESET forces ORE to 1.
D2
(Read)
IRF
Input Data Register Full — IRF is a status bit used in conjunction port
handshaking (an unsupported mode.) In normal operation, IRF is forced to 1.
IRF is a read-only bit; writes to it are ignored.
D1
(Read)
PMF
Pattern Match Flag — The PMF is a status bit set to 1 when a pattern match
is detected. If the port is a bit port, PMF is not latched. It reflects the state of
the pattern match logic just before it is read. This bit is updated every second
PCLK cycle while the CIO is in State 0. If the port pattern match logic is not
enabled (PMS1 = PMS0 = 0), PMF is forced to 0. This is a read-only bit.
Writes to it are ignored.
D0
(Read/
Write)
IOE
Interrupt on Error — While IOE is cleared to 0, error conditions in bit ports
using pattern-recognition logic (a second match before a previous match is
acknowledged) are ignored. However, if IOE is 1, such errors will cause IP to
be set and will halt normal operation of the port until the error condition is dealt
with.
