I/O Port Operation
92 – CIO Chip
VL-486-4 Reference Manual
I/O Port Operation
O
VERVIEW
There are three I/O ports provided by the CIO device. Ports A and B are general-purpose ports;
Port C is a 4-bit special-purpose port. All three ports can be programmed as bit ports.
In general, bit ports are used to provide status input lines and control output lines. When the I/O
ports are configured as bit ports, data can be moved in either direction on an individual, pin-by-
pin basis. There are up to twenty pins available for this kind of data handling by the three ports.
Another I/O Port function is to provide external access for the control of three independent
counter/timers and distribution of their outputs. Port B provides access for Counter/Timers 1 and
2. Port C provides access to Counter/Timer 3.
Pattern-recognition capability is provided in Ports A and B. In general, it is possible to test data
for specified patterns and to generate interrupt requests based on the match obtained.
P
ATTERN
-R
ECOGNITION
L
OGIC
O
PERATION
Both Ports A and B can be programmed to generate interrupts when a specific pattern is
recognized at the port. The pattern-recognition logic is independent of the port application,
thereby allowing the port to recognize patterns in all of its configurations. The pattern can be
independently specified for each bit as: 1, 0, 0-to-1 transition, 1-to-0 transition, or any transition.
Individual bits can be masked off. Three modes of pattern-recognition operation are supported:
AND, OR, and OR-Priority Encoded Vector (OR-PEV). A pattern match is defined as the
simultaneous satisfaction of all non-masked bit specifications in the AND mode or the
satisfaction of any non-masked bit specifications in either the OR or OR-PEV modes.
The pattern specified in the Pattern Definition register assumes that the data path is programmed
to be non-inverting. If an input bit in the data path is programmed to be inverting, the pattern
detected is the opposite of the one specified. Output bits used in the pattern of match logic are
internally sampled before the invert/non-invert logic.
The operation of the pattern-recognition logic in the various port modes will be described in
detail in the following sections.
B
IT
P
ORT
O
PERATION
Bit ports are used to provide the CPU with input lines to monitor status, and with output lines to
provide control. There are up to twenty bits available for this type of data handling provided by
the three ports of the CIO: eight each by Ports A and B and four by Port C.
Writing the data register of a bit port updates the value being output by all output bits in the port.
Reading the data register of the bit port returns the state of all bits, outputs as well as inputs.
B
IT
P
ORT
S
IMPLE
O
PERATION
The port’s Data Direction register specifies the direction of data flow for each bit of a bit port. A
1 specifies an input bit; a 0 specifies an output bit.
