Counter/Timer Operation
VL-486-4 Reference Manual
CIO Chip – 95
Table 63: Counter/Timer External Access
Function
Counter/Timer 1
Counter/Timer 2
Counter/Timer 3
Counter/Timer Output
Port B Data 4
Port B Data 0
Port C Data 0
Counter Input
Port B Data 5
Port B Data 1
Port C Data 1
Trigger Input
Port B Data 6
Port B Data 2
Port C Data 2
Gate Input
Port B Data 7
Port B Data 3
Port C Data 3
C
OUNTER
/T
IMER
S
EQUENCE
O
F
E
VENTS
The following discussion assumes that the inputs and outputs are programmed non-inverting.
I
NITIALIZING THE
C
OUNTER
/T
IMER
Before starting a counter/timer sequence:
First, the Counter/Timer Mode Specification register and the Counter/Timer Command and
Status register of the desired counter/timer must be initialized. Initialization requires several
things to be specified, for example, the external lines to be used, the output duty cycle, and
whether the cycle is continuous or single-cycle.
Second, the Time Constant must be specified by writing the desired value to the Time Constant
register. The Time Constant register is accessed as two 8-bit registers. The registers are readable
as well as writeable, and can be accessed in any order. A 0 in the Time Constant register
specifies a Time Constant of 65,536.
Third, if external access is going to be provided, the port to be used must be programmed as a bit
port and the necessary bits must be programmed in the proper direction.
Finally, the Counter/Timer Enable bit in the Master Configuration Control register is set. This
initialization sequence can best be understood by examining the function of the various enable
bits. This bit, while cleared to 0, prevents spurious counter/timer operation:
•
IPs can not be set
•
Counter/Timers can not be triggered.
•
The Read Current Count bit that freezes the value in the Current Count register will
be held cleared to 0.
•
The Counter/Timer output is forced to 0.
Clearing an enable bit will not clear an existing IP that is set—it will only inhibit the IP from
being set again. Clearing the enable bit will clear the Read Counter Control bit, causing the
Current Count register to follow the down-counter.
