vii.
J6 – DMA Control Signals Connector................................................................. 54
L1 – Speaker Connector ...................................................................................... 55
5. Register Descriptions
.......................................................................................................... 57
Introduction ...................................................................................................................... 57
Register Summary ............................................................................................................ 57
Direct Memory Access — Channel 1.................................................................. 58
Direct Memory Access — Channel 2.................................................................. 59
Direct Memory Access — Page Registers .......................................................... 59
COM1 Serial Port ................................................................................................ 60
COM2 Serial Port ............................................................................................... 60
LPT1 Parallel Port .............................................................................................. 61
Chipset Registers ................................................................................................. 61
Floppy Disk Drive Controller.............................................................................. 62
IDE Hard Disk Drive Controller ......................................................................... 62
Interrupt Controller — Master............................................................................. 63
Interrupt Controller — Slave............................................................................... 63
Counter/Timers.................................................................................................... 64
Miscellaneous ...................................................................................................... 64
CIO Chip.............................................................................................................. 64
Special Control Register...................................................................................... 65
Watchdog Timer Hold-Off Register.................................................................... 66
Map and Paging Control Register ....................................................................... 67
6. CIO Chip
.................................................................................................................................. 69
Introduction ...................................................................................................................... 69
Features................................................................................................................ 70
Overview.............................................................................................................. 70
I/O Ports............................................................................................................... 70
Ports A and B....................................................................................................... 70
Port C ................................................................................................................... 71
Counter/Timers.................................................................................................... 71
Interrupt Control Logic........................................................................................ 71
Register Description ......................................................................................................... 71
Introduction ......................................................................................................... 71
CIO Registers ...................................................................................................... 72
Register Access.................................................................................................... 73
State 0 .................................................................................................................. 73
State 1 .................................................................................................................. 73
Master Control Registers .................................................................................................. 74
Master Interrupt Control Register ....................................................................... 74
Master Configuration Control Register ............................................................... 76
Port Mode Specification Register........................................................................ 78
Port Handshake Specification Registers........................................................................... 79
Port A/B Handshake Specification Registers ...................................................... 79
Port Command and Status Registers ................................................................... 79
Bit Path Definition Registers............................................................................................ 81
Data Path Polarity Registers ................................................................................ 81
Data Direction Registers...................................................................................... 81
