Counter/Timer Operation
98 – CIO Chip
VL-486-4 Reference Manual
C
OUNTER
/T
IMER
O
UTPUT
There are three duty cycles available for the timer/counter output: pulse, one-shot, and square-
wave. When the Pulse mode is specified, the output goes High for one cycle, beginning when the
down-counter leaves the count of 1. In the One-shot mode, the output goes High when the
counter/timer is triggered and goes Low when the down-counter reaches 0. When the square-
wave output duty cycle is specified, the counter/timer goes through two full sequences for each
cycle. The initial trigger causes the down-counter to be loaded and the normal count-down
sequence to begin. When a 1 count is detected on the down-counter’s clocking edge, the output
goes High and the time constant value is reloaded. On the clocking edge, when both the down-
counter and the output are 1’s, the output is forced Low.
L
INKED
S
EQUENCE
Counter/Timers 1 and 2 can be linked internally in three different ways. Counter/Timer 1’s
output (inverted) can be used as Counter/Timer 2’s trigger, gate, or counter input. When linked,
the counter/timers have the same capabilities as when used separately. However, when they are
linked, they should be linked before they are enabled. The only restriction is that when
Counter/Timer 1 drives Counter/Timers 2’s count input, Counter/Timer 2 must be programmed
with its external count input disabled (ECE = 0).
The initialization procedure, then, is the same as for individual counter/timers, except that the
linking bits need to be appropriately set.
