CIO Initialization
VL-486-4 Reference Manual
CIO Chip – 101
I
NTERRUPT
O
PERATION
The IP bit is not set while the CIO Chip is in State 1 (refer to page 79 for a description of state
conditions.) Therefore, to minimize interrupt latency, the CIO Chip should not be left in State 1.
The CIO Chip generates an interrupt request on INT 15 if:
•
Interrupt requests are enabled (IE = 1 and MIE = 1)
•
It has an interrupt pending (IP = 1)
•
It does not have an interrupt under service (IUS = 0)
•
No higher-priority interrupt is being serviced (IEI = 1)
To remove the interrupt request signal, the IP bit for the associated interrupt needs to be cleared.
CIO Initialization
I
NTRODUCTION
The CIO is reset by writing a 1 to the Reset bit (D0) in the Master Interrupt Control register.
RESET disables all functions except a read or write to the Reset bit. In the reset state, the pointer
always points to the Master Interrupt Control register. Writes to all other bits are ignored, and all
reads return 01h. In this state, all control bits are forced to 0, all port I/O lines are tri-stated, and
the interrupt output is not asserted.
Even if the state of the CIO is not known, the following sequence will reset it.
IN
CIOCTL
Insures state 0 or reset state
OUT
CIOCTL,0
Write pointer or clear reset
IN
CIOCTL
State 0
OUT
CIOCTL,0
Write pointer
OUT
CIOCTL,1
Write reset
OUT
CIOCTL,0
Clear reset
