Programming
102 – CIO Chip
VL-486-4 Reference Manual
E
NABLE
B
ITS
O
PERATION
As the different functions of the CIO are being initially programmed, it is possible for erroneous
interrupt requests to be generated, or for an illegal combination of modes to be temporarily
specified. To alleviate this problem without imposing severe restrictions on the sequence of
events required to initialize the device, five internal enable control bits are provided: Port A
Enable, Port B Enable, Counter/Timer 1 Enable, Counter/Timer 2 Enable, and one enable shared
by Counter/Timer 3 and Port C. While these bits are cleared to 0, the corresponding logic
sections are in an initialization mode. All of the registers can be read and written, but the normal
operation of the sections is inhibited. The Port A and Port B Enables, when cleared to 0, force
their respective I/O lines into a high-impedance state, hold the 1's catchers in a reset condition,
inhibit request/wait generation, and prevent the setting of their Interrupt Pending (IP) bits (the
states of IP and Interrupt Under Service (IUS) are not affected). Additionally, output data can be
written (the first data output is valid when the output drivers go active), but the data direction for
these bits must be properly specified before the data is written. The Port C Enable operates in the
same way, and, until set to 1, the handshake logic for Ports A and B is forced into an idle state.
The Counter/Timer Enables, when set to 0, terminate any countdown sequence in progress,
inhibit the counter/timer from being triggered, and force the counter output to 0. While the
enable is 0, the Read Counter Control (RCC) bit in the Counter/Timer Command and Status
register is forced to 0. Independent enable bits are provided for the different sections of the
device so that the individual sections can be reconfigured without disturbing the status of the
unchanged sections. By using these enable bits, the device can be initialized in any sequence as
long as the desired configuration for a section is specified before its enable bit is set to 1. When
ports or counter/timers are to be linked, the bits which specify linking must be programmed
before the functions are enabled. In this case two writes are required to the Master Configuration
Control register.
Programming
Programming the CIO Entails loading control registers with bits to implement the desired
operation. As discussed above, individual enable bits are provided for the various major blocks
so that erroneous operations do not occur while the port is being initialized. Before the ports are
enabled: IPs cannot be set, REQUEST and WAIT cannot be asserted, and all output remain high
impedance; the handshake lines are ignored until Port C is enabled; and the counter/timers
cannot be triggered until their enable bits are set.
