Register Description
VL-486-4 Reference Manual
CIO Chip – 73
R
EGISTER
A
CCESS
The registers in the CIO chip are accessed in a two-step sequence:
1. Write the register index value to the Control port (00E4h)
2. Read or write the register data from/to the Control port (00E4h)
Since only one I/O port is used, internal logic must decide if data is meant for the Index register
or an internal control register. Direct accesses of the data registers has no effect on the indexing
mechanism.
S
TATE
0
•
Data written to the Control port (00E4h) goes to the Index register. The logic
switches to state 1.
•
Data read from the Control port (00E4h) comes from the Index register. The logic
remains in state 0.
S
TATE
1
•
Data written to the Control port (00E4h) goes to the internal control register pointed
to by the Index register. The logic reverts back to state 0.
•
Data read from the Control port (00E4h) comes from the internal control register
pointed to by the Index register. The logic reverts back to state 0.
For example, to read the Current Vector register:
OUTPUT
00E4h,1Fh
;Write 1Fh to the Index register
INPUT
00E4h
;Read the value of the Current Vector register
In state 1, many internal operations are suspended, Interrupt Pending (IP) cannot be set, and
internal status is frozen. Therefore, to minimize interrupt latency and to allow continuous status
updates, the CIO chip should not be left in State 1.
All data access must be performed as a two byte transaction. The data registers for Ports A, B,
and C can be accessed using this indexed method, however, for higher throughput, the data
registers can be directly addressed using the following I/O port addresses:
Table 50: Port A/B/C Direct Access Addresses
Register
Address
Port A Data Port
00E5h
Port B Data Port
00E6h
Port C Data Port
00E7h
