Interrupt Operation
100 – CIO Chip
VL-486-4 Reference Manual
I
DENTIFICATION OF THE
H
IGHEST
-P
RIORITY
I
NTERRUPT
R
EQUEST
Since CIO hardware interrupt vectors are not supported on the VL-486-4, the Current Vector
register facilitates the identification of the interrupting source. When read, the data returned is
the same as the interrupt vector that would normally be provided during an Interrupt
Acknowledge cycle based on the highest IP set. If no unmasked IPs are set, the value FFh is
returned. The Current Vector register provides an easy way to poll all IPs in a single read.
The interrupt vector can include additional status information identifying the cause of the
interrupt as well as the source identification.
The CIO contains three vector registers: one for Port A, one for Port B, and one shared by the
three counter/timers. Unique identification information can be placed by the user in the Interrupt
Vector register for each interrupt source. The base vector can be modified to include status
information to pinpoint the cause of the interrupt. A Vector Includes Status (VIS) control bit
controls whether or not the vector is modified with status information.
Each base vector has its own VIS bit and is controlled independently. When MIE = 1, reading
the base vector register always includes status, independent of the state of the VIS bit. All the
information obtained by the vector, including status, can thus be obtained with one additional
instruction when VIS is set to 0. When MIE = 0, reading the vector register returns the
unmodified base vector so that it can be verified.
Another register, the Current Vector register, facilitates the use of the CIO in a polled
environment. When read, the data returned is the same as the interrupt vector that would
normally be output as a hardware interrupt vector. If no unmasked IPs are set, the value FFh is
returned.
The No Vector (NV) control bit of the Master Interrupt Control register, when set to 1, inhibits
the generation of an interrupt vector during an INTAK cycle. The NV bit does not affect the
setting of the IUS operation.
Table 64: Interrupt Vector Encoding if Vector Includes Status
Port Vector Status
OR-Priority Encoded
Vector Mode
All Other Modes
Counter/Timer Status
D3 D2 D1
x
x
x
Number of highest
priority bit with a match.
D3 D2 D1
ORE
IRF
PMF
Normal
0
0
0
Error*
D2 D1
0
0
Counter/Timer 3
0
1
Counter/Timer 2
1
0
Counter/Timer 1
1
1
Error
* The error status indicates that the highest-priority counter/timer with an interrupt pending also
has its ERR flag set. The CPU must poll the Command and Status registers to determine which
counter/timer has its ERR flag set.
