Introduction
70 – CIO Chip
VL-486-4 Reference Manual
F
EATURES
The CIO device satisfies a wide range of applications because of its extensive list of features:
•
Two independent 8-bit, double-buffered, bi-directional I/O ports, plus a 4-bit
special-purpose I/O ports. The I/O ports feature programmable polarity,
programmable direction (Bit mode), 1's catchers, and programmable open drain
outputs.
•
Flexible pattern-recognition logic, programmable as a 16-vector interrupt controller.
•
Three independent 16-bit counter/timers, each with three output duty cycles (pulsed,
one-shot, and square-wave) and up to four external access lines (count input, output,
gate, and trigger). The counter/timers are programmable as retriggerable or non-
retriggerable.
•
Registers are accessed in two steps using an Index register.
O
VERVIEW
The CIO consists of three I/O ports (two general-purpose 8-bit ports and one special purpose 4-
bit port), three 16-bit counter/timers, and an interrupt control logic block. A large number of
programmable options allow you to tailor the configuration to suit specific applications.
I/O P
ORTS
There are three I/O ports: two general-purpose 8-bit ports (which are linkable into one 16-bit
port), and one special-purpose 4-bit port.
P
ORTS
A
AND
B
The two general-purpose 8-bit I/O ports, Ports A and B, are identical, except that Port B can be
programmed to provide external access to Counter/Timers 1 and 2. Either port can be
programmed to be a control port with the direction of each bit individually programmable.
Both ports include pattern-recognition logic, which allows interrupt generation when a specific
pattern is detected. The reference pattern for the pattern-recognition logic is specified by the
contents of three registers: the Pattern Polarity register, Pattern Transition register, and Pattern
Mask register. The detailed characteristics of each bit path (for example, the direction of data
flow or whether a path is inverting or non-inverting) are programmed using the Data Path
Polarity register, Data Direction register, and Special I/O Control register.
For each port, the primary control and status bits are grouped in a single register, the Command
and Status register. After the port is configured, this is the only register that needs to be accessed
frequently. To facilitate initialization, the port logic is designed so that registers associated with
an unrequired capability are ignored and do not have to be programmed.
