Terasic TR-5 Lite FPGA, Руководство пользователя

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TR5-Lite User Manual 73 www.terasic.com
June 20, 2018
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Function Block Diagram
Figure 6-1 shows the function block diagram of the demonstration. The four QDRII+ SRAM
controllers are configured as a 72Mb controller. The QDRII+ SRAM IP generates a 550MHz clock
as memory clock and a half-rate system clock, 275MHz, for the controllers.
Figure 6-1 Function Block Diagram of the QDRII+ SRAM x4 Demonstration
In this demonstration, four QDRII+ SRAM controllers are sharing the FPGA resources (OCT, PLL,
and DLL), and the QDRII+ SRAM (C) is configured as the master to share the resource to the other
three slave QDRII+ SRAM (A/B/D). RW_test modules read and write the entire memory space of
each QDRII+ SRAM through the Avalon interface of each controller. In this project, the Avalon bus
read/write test module will first write the entire memory and then compare the read back data with
the regenerated data (the same sequence as the write data). Test control signals for four QDRII+
SRAMs will generate from BUTTON0 and four LEDs will indicate the test results of four QDRII+
SRAMs.