Terasic TR-5 Lite FPGA, Руководство пользователя

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TR5-Lite User Manual 25 www.terasic.com
June 20, 2018
FSM_D24 Data bus 2.5-V
PIN_BC32
FSM_D25 Data bus 2.5-V
PIN_AM29
FSM_D26 Data bus 2.5-V
PIN_BD32
FSM_D27 Data bus 2.5-V
PIN_AY30
FSM_D28 Data bus 2.5-V
PIN_AY31
FSM_D29 Data bus 2.5-V
PIN_AN28
FSM_D30 Data bus 2.5-V
PIN_AL30
FSM_D31 Data bus 2.5-V
PIN_AL31
FLASH_CLK Clock 2.5-V PIN_AU31
FLASH_RESET_n Reset 2.5-V PIN_AV31
FLASH_CE_n[0] Chip enable of of flash-0 2.5-V PIN_AJ31
FLASH_CE_n[1] Chip enable of of flash-1 2.5-V PIN_AW32
FLASH_OE_n Output enable 2.5-V PIN_AU30
FLASH_WE_n Write enable 2.5-V PIN_AH30
FLASH_ADV_n Address valid 2.5-V PIN_AT29
FLASH_RDY_BSY_n[0] Ready of flash-0 2.5-V PIN_AJ30
FLASH_RDY_BSY_n[0] Ready of flash-1 2.5-V PIN_AV32
2
2
.
.
8
8
D
D
D
D
R
R
3
3
S
S
D
D
R
R
A
A
M
M
The development board supports two independent banks of DDR3 SDRAM which totals 2GB in
memory. Each bank comprises of two x8 DDR3 devices. The DDR3 signals are connected to the
vertical I/O banks on the bottom edge of the FPGA. The DDR3 devices shipped with this board are
running at 667 MHz, for a total theoretical bandwidth of over 42.68 Gbps. Figure 2-9 shows the
connections between the DDR3 and Stratix V GX FPGA.