Terasic TR-5 Lite FPGA, Руководство пользователя

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TR5-Lite User Manual 72 www.terasic.com
June 20, 2018
Chapter 6
Memory Reference Design
The TR5-Lite development board includes two kinds of high-speed memories:

DDR3 SDRAM: two independent banks, update to 667 MHz

QDRII+ SRAM: four independent banks, update to 550 MHz
This chapter will show three examples which use the Altera Memory IP to perform memory test
functions. The source codes of these examples are all available on the TR5-Lite System CD. These
three examples are:

QDRII+ SRAM Test: Full test of the four banks of QDRII+ SRAM

DD3 SDRAM Test: Random test of the two banks of DDR3 SDRAM.

DDR3 SDRAM Test by Nios II: Full test of one bank of DDR3 SDRAM with Nios II
Note. 64-Bit Quartus 11.1 SP1 or later is strongly recommended for compiling these projects.
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QDR II/QDR II+ SRAM devices enable you to maximize memory bandwidth with separate read
and write ports. The memory architecture features separate read and write ports operating twice per
clock cycle to deliver a total of four data transfers per cycle. The resulting performance increase is
particularly valuable in bandwidth-intensive and low-latency applications.
This demonstration utilizes four QDRII+ SRAMs on the TR5-Lite board. It describes how to use
Altera’s “QDRII and QDRII+ SRAM Controller with UniPHY” IP to implement a memory test
function. In the design, the four QDRII controllers share the same PLL/DLL/OCT due to limited
DLL numbers in the FPGA.