Si5345-44-42-D-RM
54
Rev. 1.0
Figure 26. I
2
C Write Operation
A read operation is performed in two stages. A data write is used to set the register address, then a data read is
performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in
Figure 27.
Figure 27. I
2
C Read Operation
The I
2
C bus supports SDA timeout for compatibility with the SMBus interfaces. The error flags are found in the
registers listed in Table 36.
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
Write Operation – Single Byte
S
0 A Reg Addr [7:0]
Slv Addr [6:0]
A
Data [7:0]
P
A
Write Operation - Burst (Auto Address Increment)
Reg Addr +1
S
0 A Reg Addr [7:0]
Slv Addr [6:0]
A
Data [7:0]
A
Data [7:0]
P
A
Host
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Host
Si5345/44/42
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
Read Operation – Single Byte
S
0 A Reg Addr [7:0]
Slv Addr [6:0]
A P
Read Operation - Burst (Auto Address Increment)
Reg Addr +1
S
1 A
Slv Addr [6:0]
Data [7:0]
P
N
S
0 A Reg Addr [7:0]
Slv Addr [6:0]
A P
S
1 A
Slv Addr [6:0]
Data [7:0]
A
P
N
Data [7:0]
Host
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Host
Si5345/44/42