Plant changes during redundant operation - H-CiR
12.9 Removal of components
CPU 410 Process Automation/CPU 410 SMART
214
System Manual, 05/2017, A5E31622160-AC
12.9.3
Opening the H-CiR wizard
The next steps, except for the conversion of the hardware, are performed by the H-CiR
wizard.
Reaction of the I/O to the new master CPU
While the previous master CPU is still in STOP, the I/O reacts to the new master CPU as
follows:
Type of I/O
One-sided I/O of the
previous master CPU
One-sided I/O of the new
master CPU
Switched I/O
The I/O modules
to be removed
1)
No longer accessed by the CPU.
Driver blocks are no longer available.
I/O modules still
available
No longer accessed by
the CPU.
Output modules have the
configured substitute or
holding values.
Newly configured
2)
and
updated by the CPU.
Continue working without
interruption.
The DP stations to
be removed
like I/O modules to be removed (see above)
1) No longer included in the hardware configuration, but still plugged
2) CPUs are also first reset. Output modules briefly have 0 (instead of the configured substitute or
holding values).
Reaction of the I/O to entering redundant mode
The fault-tolerant system is in redundant mode with the new configuration. The I/O reacts as
follows:
Type of I/O
One-sided I/O of the
reserve CPU
One-sided I/O of the
master CPU
Switched I/O
The I/O modules
to be removed
1)
No longer accessed by the CPU.
Driver blocks are no longer available.
I/O modules still
available
Newly configured
2)
and
updated by the CPU.
Continue working without interruption.
The DP stations to
be removed
like I/O modules to be removed (see above)
1) No longer included in the hardware configuration, but still plugged
2) CPUs are also first reset. Output modules briefly have 0 (instead of the configured substitute or
holding values).
Reaction to exceeding the monitoring times
When one of the monitored timers exceeds the configured maximum value, the update is
aborted and no master switchover is performed. The H system remains in solo mode with
the previous master CPU and attempts to later perform the master switchover under certain
conditions. For details, refer to the section Time monitoring (Page 120).