Supplementary information
18.16 CPU 410 cycle and reaction times
CPU 410 Process Automation/CPU 410 SMART
372
System Manual, 05/2017, A5E31622160-AC
Calculating the cycle time
The theoretical cycle time for the example is derived from the following times:
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As the CPU-specific factor is 1.2, the user program execution time is:
approx. 12.0 ms
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Process image transfer time (4 x double-word access and 3 x word access)
Process image: 9 µs + 7 ×25 µs = approx. 0.184 ms
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Operating system runtime at scan cycle checkpoint:
approx. 0.31 ms
The total of the listed times is equivalent to the cycle time:
Cycle time = 12.0 ms + 0.184 ms + 0.31 ms = 12.494 ms.
Calculation of the actual cycle time
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Allowance for communication load:
12.494 ms * 100 / (100–40) = 20.823 ms.
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A time-of-day interrupt with a runtime of 0.5 ms is triggered every 100 ms.
The interrupt can be triggered a maximum of one time during a cycle:
0.5 ms + 0.490 ms (from table 16-9) = 0.99 ms.
Allowing for communication load:
0.99 ms * 100 / (100–40) = 1.65 ms.
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20.823 ms + 1.65 ms = 22.473 ms.
Taking into account the time slices, the actual rounded up cycle time is 22.5 ms.
Calculating the longest response time
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Longest response time
22.5 ms * 2 = 45 ms.
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Delay of inputs and outputs
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The maximum input delay of the digital input module SM 421; DI 32×DC 24 V is 4.8
ms per channel
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The output delay of the digital output module SM 422; DO 16×DC 24 V/2A is
negligible.
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An interference frequency suppression of 50 Hz was assigned for the analog input
module SM 431; AI 8×13Bit. The result is a conversion time of 25 ms per channel. As
8 channels are active, a cycle time of the analog input module of 200 ms results.
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Analog output module SM 432; AO 8×13Bit was assigned for measuring range 0 ... 10
V. This results in a conversion time of 0.3 ms per channel. Since 8 channels are
active, the result is a cycle time of 2.4 ms. The transient time for a resistive load of 0.1
ms must be added to this. The result is an analog output response time of 2.5 ms.
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All components are installed in the central controller, so DP cycle times can be ignored.