RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
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Table 3-1. Interface Memory Bit Definitions (Cont'd)
Mnemonic
Location
Default
Name/Description
PRDET
1D:4
–
Rate Sequence Detection. When status bit PRDET is a 1, the modem receiver has detected a rate
sequence pattern containing a proper synchronization bit pattern. (V.17 or V.33 modes.)
RA
1A:0
0
Relay A Active. When control bit RA is a 1, the ~OH output is activated to close the normally open relay
(off-hook); when RA is a 0, the ~OH is turned off to allow the normally open relay to open (on-hook).
Note: The host has exclusive control of ~OH output through the RA bit. The delay between activation
and actual toggling of the external control line will be two sample periods.
RB
1A:1
0
Relay B Active. When control bit RB is a 1, the ~TALK output is activated to open the normally closed
relay (data); when RB is a 0, the ~TALK is turned off to allow the normally closed relay to close (talk).
Note: The host has exclusive control of ~TALK output through the RB bit. The delay between activation
and actual toggling of the external control line will be two sample periods.
RI
17:2
0
Ring Indicator. Status bit RI is set when a valid ringing signal is being detected. RI is reset when a valid
ringing signal is not being detected.
Ringing is selected if pulses are present on GPI7 input in the 15-68 Hz frequency range (default
frequency range) for the 8000 Hz sampling rate modes. The RI bit follows the ringing signal with a 1
during the ON time and a 0 during the OFF time. The minimum and maximum valid ring frequencies are
host programmable in DSP RAM. The RI bit is cleared to 0 when the RA bit = 1.
RMM
07:5
0
Room Monitor. In Voice Codec and Audio Codec modes, setting bit RMM enables the room monitor
that routes the IIA Mic input signal to the IIA Line output. Setting both CODECS and RMM bits enables
the room monitor that routes the XIA Mic input signal to the IIA Line output. The setting of the RMM bit
must be followed by the setting of the SETUP bit to become active.
RTSP
07:7
0
Request To Send Parallel. The one state of control bit RTSP begins a transmit sequence. The modem
will continue to transmit until RTSP is reset to a 0 (or ~RTS is turned off) and the turn-off sequence has
been completed. RTSP parallels the operation of the ~RTS hardware input pin. These inputs are “ORed”
by the modem, except in the Voice Codec and Audio Codec modes.
RX
0D:7
–
Receive State. In high speed modes, the modem is in the receive state when status bit RX is a 1; the
modem is in the transmit state when RX is a 0.
SBAD1L
02:0-7
--
Single Bank RAM Address 1 LSB. When control bits ACC1 and SBRAM1 are both a 1, SBAD1L
contains the LSB of the address used to access the modem's single bank RAM via the Y RAM Data 1
LSB and MSB words (00:0-7 and 01:0-7, respectively).
SBAD1M
03:0-7
--
Single Bank RAM Address 1 MSB. When control bits ACC1 and SBRAM1 are both a 1, SBAD1M
contains the MSB of the address used to access the modem's single bank RAM via the Y RAM Data 1
LSB and MSB words (00:0-7 and 01:0-7, respectively).
SBAD2L
12:0-7
--
Single Bank RAM Address 2 LSB. When control bits ACC2 and SBRAM2 are both a 1, SBAD2L
contains the LSB of the address used to access the modem's single bank RAM via the Y RAM Data 2
LSB and MSB words (10:0-7 and 11:0-7, respectively).
SBAD2M
13:0-7
--
Single Bank RAM Address 2 MSB. When control bits ACC2 and SBRAM2 are both a 1, SBAD2M
contains the MSB of the address used to access the modem's single bank RAM via the Y RAM Data 2
LSB and MSB words (10:0-7 and 11:0-7, respectively).
SBRAM1
1A:6
0
Single Bank RAM Access 1. When control bit SBRAM1 is a 1, the modem accesses the single bank
RAM associated with the address in SBAD1M and SBAD1L (BR1, CR1, DR1, IO1, and AREX1 must be
0). WRT1 determines if a read or write is performed.
SBRAM2
1A:7
0
Single Bank RAM Access 2. When control bit SBRAM2 is a 1, the modem accesses the single bank
RAM associated with the address in SBAD2M and SBAD2L (BR2, CR2, DR2, IO2, and AREX2 must be
0). WRT2 determines if a read or write is performed.
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