Rockwell RFX144V24-S23, Руководство дизайнера

Страница: 53 / 198

RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
1070 3-19
3.2 SOFTWARE INTERFACE CONSIDERATIONS
3.2.1 Parallel Data Transfer
Register 10 in the interface memory is the Data Buffer (DBUFF). The modem and host synchronize parallel data transfer by
observing the state of the Buffer 2 Available bit, B2A (1E:3). RAM Access 2 is not available when the modem is in parallel
data mode.
Receiving Parallel Data
In the parallel data mode (PDM = 1), the modem writes to register DBUFF every eight bit times. The modem sets the B2A bit
when received data is available. The host resets the B2A bit by reading DBUFF. After the modem sets B2A, the host must
respond within eight bit times or else the modem writes over register DBUFF.
While receiving, if the energy drops below the turn-off threshold for a sufficient period of time, the modem writes the last bits
of received data to register DBUFF before terminating the receive process.
The modem writes the first bit of received data to the least significant bit of register DBUFF, and writes the last bit of
received data to the most significant bit of register DBUFF.
Transmitting Parallel Data
The modem reads register DBUFF every eight bit times when transmitting. The modem sets the B2A bit when requesting
transmit data. The host resets the B2A bit by writing to DBUFF. After the modem sets B2A, the host must respond within
eight bit times or else the modem retransmits the data in register DBUFF.
If RTSP bit is reset, or SETUP bit is set while transmitting, the modem sends all of the data previously read from register
DBUFF before terminating the transmit process.
The modem transmits the least significant bit of register DBUFF first, and transmits the most significant bit of register DBUFF
last.
The flowchart shown in Figure 3-2 may be used for parallel data transfer.
3.2.2 Programmable Interrupt Feature
The interface memory interrupt feature enables the host to select an interrupt to occur on any combination of bits within an
interface memory register. This feature is not available in Full-Duplex Speakerphone mode (CONF = 91h).
Programmable Interrupt Bits
The programmable interrupt routine runs at the sample rate in all transmit and receive modes if PIDR is a 0. The
programmable interrupt can run at the data rate in high speed and FSK modes if PIDR is a 1. If the host sets the
Programmable Interrupt Enable bit, PIE (1F:4), the modem sets the Programmable Interrupt Active bit, IIA (1F:7), and
~IRQ1 goes low when the interrupt condition is true. The Programmable Interrupt Request bit, PIREQ (1F:3), is set by the
modem whenever the interrupt condition is true. The host must reset PIREQ after servicing the interrupt since the modem is
unable to reset this bit.
An interrupt may occur only within a single interface memory register based upon any combination of bits. For example, the
host may select register 09h and generate an interrupt whenever bits 09:7, 09:4, and/or 09:3 are set, but may not select bits
08:7 and 09:2 to generate an interrupt. The register is selected by specifying the Interrupt Address, ITADRS (0A:0-4). (See
ITADRS in Table 3-1.)
The Interrupt Bit Mask register, ITBMSK (0B:0-7), selects the bits to be tested in the interface memory register specified by
ITADRS. For example, if ITBMSK is equal to FFh, all the bits are selected; if ITBMSK is equal to 0Fh, the four least
significant bits are selected.
Programmable Interrupt Operating Modes
There are two operating modes (AND or OR) with each mode having four trigger options. The ANDOR bit selects the
operating mode. The TRIG bits (0A:6-7) select the triggering option. (See ANDOR and TRIG bits in Table 3-1).