Rockwell RFX144V24-S23, Руководство дизайнера

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RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
3-26 1070
Caller ID Setup
Set CONF = 22h
Set V23HDX = 0,
ANS = 0
(Rx = 1200 bps)
Set SETUP bit
Exit
Figure 3-6. Caller ID Mode Setup Procedure
3.2.9 High Speed Timing
Several status bits in the DSP interface memory are useful to the host for monitoring various receiver conditions. These bits
are significant during training and data reception/transmission. Figure 3-7 illustrates the timing relationships between these
bits. Table 3-2 lists the timing values.
Table 3-2. High Speed Status Bit Timing
Mode T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11** T13 Units
V.33 & V.17 Long 187.5 20.0 106.7 1240 26.7 20.0 6.3 4.2 10.9 13 20 40 ms
V.33 & V.17 Short 187.5 20.0 106.7 15.8 0* 20.0 4.6 4.2 10.9 13 20 40 ms
V.29 Long 187.5 20.0 53.3 160 0 20.0 6.3 4.2 4.2 5 20 34 ms
V.29 Short 187.5 20.0 41.7 25.8 0 7.5 4.6 4.2 4.2 5 20 34 ms
V.27 ter, 4800 Long 187.5 20.0 31.2 671 0 5.0 9.4 6.3 6.3 7 20 19 ms
V.27 ter, 4800 Short 187.5 20.0 8.8 36.3 0 5.0 3.1 6.3 6.3 7 20 19 ms
V.27 ter, 2400 Long 187.5 20.0 41.6 895 0 6.6 12.5 8.3 8.3 10 20 24 ms
V.27 ter, 2400 Short 187.5 20.0 11.7 48.3 0 6.6 4.2 8.3 8.3 10 20 24 ms
Notes:
* SHPR = 0; T5 = 26.5 ms for SHPR = 1.
** 140 ms if SQEXT = 1.
*** In parallel mode data mode with HDLC bit off, turning ~RTS off immediately after loading the last byte (see Section 3.2.1): T12 = 8 bit
times.
In parallel mode data mode with HDLC bit on, turning ~RTS off immediately after loading the last byte (see Section 5): T12 = 32 bit times.