RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
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Table 3-1. Interface Memory Bit Definitions (Cont'd)
Mnemonic
Location
Default
Name/Description
AREX1
05:6
0
RAM Access 1 Code Extension Select. When control bit AREX1 is a 1, the upper part (80h-FFh) of
the RAM is selected. When AREX1 is a 0, the lower part (0-7Fh) is selected.
AREX2
15:6
0
RAM Access 2 Code Extension Select. When control bit AREX2 is a 1, the upper part (80h-FFh) of
the RAM is selected. When AREX2 is a 0, the lower part (0-7Fh) is selected.
ASPEED
1D:6
0
Auto Speed Change Enable. When control bit ASPEED is a 0, the modem transmitter sends the
default V.17 rate sequence. The modem receiver stores the rate sequence in RAM. (V.17 modes.)
ASPEED
Data Rate
Rate Sequence Pattern
0
V.17, all rates
0111h
1
14400 bps
0171h
1
12000 bps
01B1h
1
9600 bps
01F1h
1
7200 bps
0331h
When set to a 1, the modem transmitter sends a different rate sequence depending on the selected
TCM configuration. When receiving in a TCM configuration, the modem reconfigures to the received rate
sequence. The new configuration is reflected in the receiver CONF register.
B1A
1E:0
–
Buffer 1 Available. When set to a 1, status bit B1A signifies that the modem has either written
diagnostic data to, or read diagnostic data from, the Y RAM DATA 1 LSB (YDAL1) register (00:0-7).
This condition can also cause ~IRQ1 or ~IRQ2 to be asserted. The host writing to or reading from
register 00 resets the B1A and B1IA bits to 0. (See B1I1E, B1I2E, and B1IA.)
B1I1E
1E:2
0
Buffer 1 Interrupt 1 Enable. When control bit B1I1E is a 1, ~IRQ1 is enabled for Buffer 1, i.e., the
modem will assert ~IRQ1 and set B1IA to a 1 when B1A is set to 1 by the modem. When B1I1E is a 0,
B1A has no effect on ~IRQ1 and B1IA. (See B1A and B1IA.)
B1I2E
1E:1
0
Buffer 1 Interrupt 2 Enable. When control bit B1I2E is a 1, ~IRQ2 is enabled for Buffer 1, i.e., the
modem will assert ~IRQ2 when B1A is set to 1 by the modem. When B1I2E is a 0, B1A has no effect on
~IRQ2. (See B1A.)
B1IA
1E:6
–
Buffer 1 Interrupt Active. When Buffer 1 interrupt is enabled (B1I1E is a 1) and B1A is set to a 1 by the
modem, the modem asserts ~IRQ1 and sets status bit B1IA to a 1 to indicate that B1A caused the
interrupt. The host writing to or reading from register 00 resets B1IA to a 0. (See B1I1E and B1A.)
B2A
1E:3
–
Buffer 2 Available. When set to a 1, status bit B2A signifies that, when the modem is in the parallel
data mode (with or without HDLC selected), it has read register 10:0-7 (DBUFF) when transmitting
(buffer becomes empty), or it has written register 10:0-7 (DBUFF) when receiving (buffer becomes full).
When the modem is not in parallel data mode, the setting of B2A to a 1 by the modem signifies that the
modem has either written diagnostic data to, or read diagnostic data from, the Y RAM DATA 2 LSB
(YDAL2) register (10:0-7).
In Voice Codec Mode (CONF = 90h or 98h) or Audio Codec Mode (CONF = 92h or 94h), the modem
sets B2A to indicate that the modem has loaded encoder output data into DBUFF (coder enabled, i.e.,
CDEN = 1 and DCDEN = 0)) or that the modem has read decoder input data from DBUFF (decoder
enabled, i.e., DCDEN = 1 and CDEN = 0).
The modem setting B2A can also cause ~IRQ1 or ~IRQ2 to be asserted. The host writing to or reading
from register 10h resets the B2A and B2IA bits to 0. (See B2I1E, B2I2E, and B2IA.)
B2I1E
1E:5
0
Buffer 2 Interrupt 1 Enable. When control bit B2I1E is a 1, ~IRQ1 is enabled for Buffer 2, i.e., the
modem will assert ~IRQ1 and set B2IA to a 1 when B2A is set to a 1 by the modem. When B2I1E is a 0,
B2A has no effect on ~IRQ1 and B2IA. (See B2A and B2IA.)
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