RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
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Table 3-1. Interface Memory Bit Definitions (Cont’d)
Mnemonic
Location
Default
Name/Description
CR1
05:0
1
Coefficient RAM 1 Select. When control bit CR1 is a 1, AREX1 and ADD1 address Coefficient RAM.
When CR1 is a 0, AREX1 and ADD1 address Data RAM. This bit must be set according to the desired
RAM address (Table 4-1).
CR2
15:0
0
Coefficient RAM 2 Select. When control bit CR2 is a 1, AREX2 and ADD2 address Coefficient RAM.
When CR2 is a 0, AREX2 and ADD2 address Data RAM. This bit must be set according to the desired
RAM address (Table 4-1).
CRC
09:1
–
Cyclic Redundancy Check Error. In HDLC mode, when status bit CRC is a 1 and status bit EOF is a
1, the received frame is in error. When CRC is a 0 and EOF is a 1, the received frame is correct. CRC
changes immediately before EOF is set to a 1.
In Caller ID mode (CONF = 22h), the modem sets the CRC bit if the stop bit is detected to be a 1.
CTSP
0F:1
–
Clear To Send Parallel. When set to a 1, status bit CTSP indicates to the DTE that the training
sequence has been completed and any data present at TXD (PDM = 0) or DBUFF (PDM = 1) will be
transmitted. CTSP parallels the operation of the ~CTS pin.
DATA
0C:5
–
Data Mode. When status bit DATA is a 1, the high speed transmitter/receiver is in the data mode.
DBUFF
10:0-7
–
Data Buffer. In the parallel data mode (PDM bit = 1), the host obtains received data from the modem by
reading a data byte from DBUFF; the host sends data to the modem to be transmitted by writing a data
byte to DBUFF. The data is received and transmitted bit 0 first.
The modem reading (taking data) or writing (sending data) to this register sets the B2A bit. The host
reading (taking data) or writing (sending data) to this register resets the B2A bit. By setting B2IxE (x=1
or 2), the host can enable the assertion of ~IRQx upon the setting of B2A. Bit 0 of DBUFF is the first bit
of the 8-bit input or output.
In the V.23 configuration (CONF = $24), in parallel data mode (PDM bit = 1), the host obtains received
data from the modem by reading a data byte from DBUFF. The modem writing (sending data) to this
register sets the B2A bit (1E:3). The host reading (taking data) from this register resets the B2A bit
(1E:3).
In voice/audio codec modes, DBUFF is the 8-bit voice/audio decoder input buffer (DCDEN = 1 and
CDEN = 0) or voice/audio coder output buffer (CDEN = 1 and DCDEN = 0).
DCABLE
08:1
0
Digital Cable Equalizer Enable. Control bit DCABLE enables (1) or disables (0) insertion of the digital
cable equalizer into the high speed receive and transmit paths.
DCDEN
1A:5
0
Decoder Enable. When control bit DCDEN is a 1 and bit CDEN is a 0, the modem performs voice/audio
decoding on the DBUFF input. The decoder output is sent to TXA1/TXA2. Status bit B2A is set by the
modem when the decoder's input buffer is empty. CDEN must be reset when DCDEN is a 1. ACC2
must be reset. (Voice/audio codec modes.)
DCVOX
14:5
0
Decouple VOX. When the voice coder Energy AGC is enabled (AGCSEL = 0) and control bit DCVOX is
a 0 , the AGC gain is applied to the input signal when the AGC is enabled (AGCDIS = 0) and the VOX
bit is a 1. When AGCSEL = 0 and DCVOX is a 1, the AGC gain is applied signal when the AGC is
enabled (AGCDIS = 0) regardless of the VOX bit state. (Voice/audio codec modes.)
DR1
05:4
0
Data Rate 1. In high speed, FSK/DTMF, or FSK modes, when control bit DR1 is a 1, RAM access
associated with ADD1 occurs at the modem data rate if BR1 = 0. When DR1 is a 0, RAM access occurs
at the modem sample rate (9600 Hz) or baud rate depending on the state of BR1.
DR2
15:4
0
Data Rate 2. In high speed, FSK/DTMF, or FSK modes, when control bit DR2 is a 1, RAM access
associated with ADD2 occurs at the modem data rate if BR2 = 0. When DR2 is a 0, RAM access occurs
at the modem sample rate (9600 Hz) or baud rate depending on the state of BR2.
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