Rockwell RFX144V24-S23, Руководство дизайнера

Страница: 65 / 198

RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
1070 4-1
4. DSP RAM ACCESS
The DSP contains 16-bit words of random access memory (RAM). Because the DSP is optimized for performing complex
arithmetic, the RAM is organized into real (X RAM) and imaginary (Y RAM) parts. The host processor can read or write both
the X RAM and the Y RAM. The DSP also contains a single bank RAM (SBADxy) which the host can read or write.
4.1 INTERFACE MEMORY ACCESS TO DSP RAM
DSP interface memory is an intermediary during data exchanges between the host and DSP RAM. The address stored in
interface memory RAM address registers by the host determines the DSP RAM address for data access.
The 16-bit words are transferred between DSP RAM and DSP interface memory either at the baud rate or at the sample rate
as selected by the BR1 and BR2 bits. The baud rate is determined by the selected configuration, but the sample rate is fixed
at 9600 Hz (8000 Hz in voice and speakerphone modes).
Two RAM Access bits in the DSP interface memory tell the DSP to access the X RAM and/or Y RAM. The transfer is
initiated by the host setting the ACC1 and/or the ACC2 bit(s). The DSP tests these bits each baud, data, or sample period,
except in voice, or tone mode, where these bits are always tested at the sample period.
4.1.1 Host Programmable Data
The DSP RAM access functions, codes, and registers are identified in Table 4-1 (X RAM and/or Y RAM) and Table 4-2
(SBRAM).
4.1.2 Host DSP RAM Read and Write Procedures
The modem main RAM has four RAM banks: Data RAM Real, Data RAM Imaginary, Coefficient RAM Real, and Coefficient
RAM Imaginary. The designation (x = 1, 2) indicates x may be replaced by either 1 or 2, with 1 and 2 referring to RAM
Access 1 and RAM Access 2, respectively.
To access the main RAM, write the desired RAM access code into ADDx and AREXx (x = 1, 2). Bits 0 through 6 and AREXx
(x = 1, 2) of the access code specify the RAM location and bit 7 of the access code specifies a real (0) or imaginary (1) RAM
location. The CRx (x = 1, 2) bit controls whether the coefficient RAM (1) or data RAM (0) is accessed.
To access single bank RAM access, write the address to SBADxM and SBADxL and set the SBRAMx bit.
4.1.3 DSP RAM Read Procedure
The DSP RAM read procedure is a 32-bit transfer from DSP RAM to the interface memory which transfers both the X RAM
and Y RAM simultaneously (Figure 4-1).
1. Before reading from the DSP, reset ACC1 and/or ACC2 to a 0, then read YDAL1 to reset B1A and/or YDAL2 to reset
B2A.
2. Reset WRT1 and/or WRT2 to a 0 to inform the DSP that a RAM read will occur when ACC1 and/or ACC2 is set to a 1.
3. For main RAM access, write the RAM address into ADD1 and AREX1 and/or ADD2 and AREX2, reset SBRAMx, then
set CR1 and IO1, and/or CR2 and IO2 to chosen values. For single bank RAM access, write the address to SBADxM
and SBADxL and set the SBRAMx bit.
4. Set ACC1 and/or ACC2 to a 1 to signal the DSP to perform the RAM read.
5. The DSP sets B1A and/or B2A after transferring the contents of RAM into the interface memory registers.
6. If B1I1E and/or B2I1E is a 1, the DSP asserts ~IRQ1 and sets B1IA and/or B2IA to a 1 to inform the host that setting of
B1A and/or B2A is the cause.
7. If B1I2E and/or B2I2E is a 1, the DSP asserts ~IRQ2 when B1A and/or B2A is a 1. B1I2E and B2I2E have no effect on
B1IA and B2IA, respectively.
8. Read XDAM1, XDAL1, YDAM1, and YDAL1; and/or XDAM2, XDAL2, YDAM2, and YDAL2; in this order. Note that
reading YDAL1 clears B1IA and/or YDAL2 clears B2IA, which causes ~IRQ1 to return high if no other interrupt requests
are pending.
9. ~IRQ2 returns high only when B1A and/or B2A are reset to 0.