RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
5-4
1070
Receiver Notes
1. EOF, ABIDL, and OVRUN should be a known value before the data appears on RXD.
2. The host resets ABIDL in the middle of receiving an abort/idle sequence.
3. A receive overrun condition has occurred.
4. J1, J2 are invalid data.
5. CRC sets and EOF sets in response to the junk data between flags.
6. ABIDL remains high due to the incoming scrambled 1’s turnoff sequence for high speed modes.
Transmitter Mode Control
1. Upon setting RTSP, the host should initialize EOF, ABIDL, ZEROC, and OVRUN to the desired values.
2. B2A is forced high approximately 3.0
µ
s before RX(0D:7) goes low.
3. The host can send multiple flags by either waiting to load data into DBUFF or by doing a diagnostics write to RAM (see
“Flag Transmition and Reception” Section). The host can then load the first byte when RX goes low for the first frame
or after setting EOF for subsequent frames.
4. Load the first byte of the next frame after setting EOF.
5. The host sets and resets ABIDL here.
6. A transmit underrun occurs here. The modem sets ABIDL. The host must reset ABIDL.
7. AEOF is a 0 in this example.
1070F5-4
RTSP
CTSP
RX
SD
B2A
~IRQx
EOF
ABIDL
ZEROC
OVRUN
FLAG
SD
~IRQx
B2A
CDET
EOF
CRC
ABIDL
OVRUN
FLAG
F D1 D2 D3 FCS F D1 FCS F D1 A A F D1 D2 D3 FCS F D1 D2 FCS F J1 J2 F F F SCR1 s
SCR1 S 0S 1S FLAGS D1 D2 D3 FCS F D1 D2 A F F D1 D2 D3 FCS F D1 A A F D1 D2 FCS F SCR1 s
1 , 7
3
3
2
5
5
6
6
4
3
2
6
1
1
4
4
a. Transmitter
b. Receiver
1 2 3 EOF 1 EOF ABIDL ABIDL 1 2 OVERUN EOF EOF EOF ABIDL
Figure 5-4. HDLC Signals Timing
Содержание RFX144V24-S23
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