Rockwell RFX144V24-S23, Руководство дизайнера

Страница: 89 / 198

RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
1070 5-7
first byte of data of the next frame into DBUFF. If the host wants to end transmission, the host must wait for EOF to return
low before turning off RTS or ~RTS.
The automatic frame ending feature can be used to more easily facilitate the use of a DMA interrupt system. With this
feature, data is transmitted as described in the above paragraph. However, when AEOF (15:5) is set by the host, the ending
of the frame occurs “automatically,” i.e., without the host having to perform any handshaking. When the host is finished
sending the data in the frame, the host should wait until EOF is set to a 1 by the modem. The modem will then send the 16-
bit FCS and at least one ending flag. When EOF is set to a 1 by the modem, the host can then load in the first byte of data
of the next frame. EOF will be set to a 0 by the modem at the beginning of flag transmission. Therefore, the underrun
condition as described in the previous paragraph is the exact same condition that causes the 16-bit FCS and ending flag to
be transmitted when AEOF is set to a 1.
In the receiver, only the information field data between flags is passed to the user through the DBUFF register by the use of
the handshaking bit B2A. The user must wait for B2A to be set by the modem and then take the data. If AEOF is 0 and the
host does not read the data within eight bit times, OVRUN will set indicating an overrun condition, and the data in DBUFF will
be overwritten by the next byte.
Furthermore, no flags, abort/idle sequence, or FCSs are given to the user via the DBUFF register. Since these fields are not
presented to the user, there is at least a 16-bit time delay in the reception of data when receiving these fields. This allows
the FCS and ending flag, continuous flags, or the abort/idle sequence to be flushed out of the internal buffers.
5.2.6 FCS and Ending Flag Transmission and Reception
If AEOF is 0, the host ends a frame by loading in his last byte of data into DBUFF, waiting until the modem has taken it (B2A
sets), and then setting EOF. After setting EOF, the host may load in the first byte of data of the next frame into DBUFF.
When the modem recognizes that the host wants to end the frame, the modem will reset EOF. To terminate data
transmission, the host may turnoff RTS or RTSP when the modem resets EOF. After resetting EOF, the modem will
automatically transmit the 16-bit FCS and at least one flag that signifies the end of the current frame and, if another frame
follows, the beginning of the next frame.
For the case when AEOF is set to a 1 (automatic end of frame), the host ends a frame by loading in the last byte of data and
waiting until EOF is set to a 1 by the modem. The host may then load in the first byte of data of the next frame. To terminate
data transmission, the host may turn off RTS or RTSP when the modem sets EOF to a 1. The modem will then automatically
transmit the 16-bit FCS and at least one flag that signifies the end of the current frame and, if another frame follows, the
beginning of the next frame. The modem will set EOF to a 0 upon sending a flag.
Upon the receipt of an ending flag in the current frame (which may also be the beginning flag of the next frame), the modem
examines the data in the FCS register and compares it to the remainder. If the FCS register remainder is correct, CRC
(09:1) is reset. Conversely, if the remainder is incorrect, the CRC bit is set. This is the only time CRC is updated (except
upon power-up). Following this determination, the modem sets EOF. Thus, once the modem sets EOF, the host can
examine CRC to determine whether or not an erred frame was received. It is left to the host to reset the EOF bit. If the user
does not reset EOF before the end of the next frame, the host will not get any indication that the following frame has ended.
Abort/Idle Sequence Transmission and Reception
An abort/idle sequence can be sent by the host setting the bit ABIDL (09:3) in the interface memory. This stops any normal
frame transmission, as well as continuous flag transmission, and sends continuous ones. After the setting of ABIDL is
detected, the modem first completes the transmission of the current byte of data. Immediately after this transmission, the
modem sends eight consecutive ones. After these eight bit times, if ABIDL is still set, eight ones are sent again. To
discontinue this sequence, ABIDL must be reset. Then, if no new data is loaded into DBUFF, continuous flags are sent. If
new data is loaded into DBUFF (B2A is reset), the modem sends a beginning flag and then the data in DBUFF. The modem
will also recognize the setting of ABIDL while transmitting the FCS, thereby allowing the receiver to recognize that the
transmitted frame should be discarded.
The modem also has the ability to send continuous zeros. To accomplish this, ABIDL and ZEROC (09:4) must be set. The
modem completes the transmission of the current byte and then sends eight consecutive zeros. After this time, if ABIDL
remains set, eight zeros are sent again. To discontinue this sequence, ABIDL must be reset or, if continuous ones are
desired, ZEROC only must be reset. However, if no new data is loaded in DBUFF and ABIDL is reset, continuous flags are
sent regardless of the state of ZEROC. Then, if new data is loaded into DBUFF (B2A is reset), the modem sends a
beginning flag and then the data in DBUFF.
The modem in HDLC mode not only continually searches for flags, but also continually searches for an abort/idle sequence.
When the receive modem encounters this data pattern, it sets the abort/idle receive bit ABIDL. It is left up to the host to
reset this bit. However, receiver processing will continue unaffected by the state of this bit.