RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
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Table 3-1. Interface Memory Bit Definitions (Cont'd)
Mnemonic
Location
Default
Name/Description
B2I2E
1E:4
0
Buffer 2 Interrupt 2 Enable. When control bit B2I2E is a 1, ~IRQ2 is enabled for Buffer 2, i.e., the
modem will assert ~IRQ2 when B2A is set to a 1 by the modem. When B2I2E is a 0, B2A has no effect
on ~IRQ2. (See B2A.)
B2IA
1E:7
–
Buffer 2 Interrupt Active. When Buffer 2 interrupt is enabled (B2I1E is a 1) and B2A is set to a 1 by the
modem, the modem asserts ~IRQ1 and sets status bit B2IA to a 1 to indicate that B2A caused the
interrupt. The host writing to or reading from register 10 resets B2IA to a 0. (See B2I1E and B2A.)
BR1
05:2
1
Baud Rate 1. In high speed modem modes, when control bit BR1 is a 1, RAM access for ADD1 occurs
at the baud rate regardless of the state of DR1. When BR1 is a 0, RAM access occurs at the sample
rate or data rate (See DR1).
The BR1 bit must be reset to 0 for tone, Voice Codec, Audio Codec, audio, or speakerphone modes.
BR2
15:2
0
Baud Rate 2. In high speed modem modes, when control bit BR2 is a 1, RAM access for ADD2 occurs
at the baud rate regardless of the state of DR2. When BR2 is a 0, RAM access occurs at the sample
rate or data rate (See DR2).
The BR2 bit must be reset to a 0 for tone, audio, or speakerphone mode.
BRKD
09:2
–
Break Detect (Parallel Mode). When set, status bit BRKD indicates that the V.23 receiver has detected
a Break sequence (continuous Space). (V.23)
BRKS
14:6
0
Break Send (Parallel Mode). When control bit BRKS is set in parallel mode, the modem will send
continuous Space. When BRKS is reset, the modem will transmit parallel data from the TBUFFER.
(V.23)
CDEN
1A:4
0
Coder Enable. In Voice Codec Mode (CONF = 90h or 98h) or Audio Codec Mode (CONF = 92h or
94h), the modem performs voice/audio coding when control bit CDEN is a 1. The coder output is placed
into DBUFF. Status bit B2A will be set by the modem when the coder output buffer becomes full
(DBUFF). ACC2 must be reset. DCDEN must be a 0 when CDEN is a 1.
CDET
0F:0
–
Carrier Detected. When status bit CDET is a 1, the receiver has finished receiving the training
sequence, or has turned on due to detecting energy above threshold, and is receiving data. When
CDET is a 0, the receiver is in the idle state or is in the process of training.
CEQ
15:3
0
Receive Compromise Equalizer Enable (1200 bps only). When control bit CEQ is set, the receiver's
digital compromise equalizer is inserted into the receive path (1200 bps receive only). The compromise
equalizer taps are programmable through RAM. (V.23)
CODECS
07:6
0
Codec Select. In Voice Codec Mode (CONF = 90h or 98h), Audio Codec Mode (CONF = 92h or 94h),
or Audio Mode (CONF = 82h or 86h) the CODECS control bit selects data input source and output
destination. When CODECS is a 1, the XIA ADC signal is recoded and the transmit signal is sent to both
the IIA and XIA DACs. When CODECS is a 0, the IIA ADC signal is recoded and the transmit signal is
sent to the IIA DAC. The setting of the CODECS bit must be followed by the setting of the SETUP bit to
become active.
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