RFX144V24-S23 and RFX96V24-S23 Modem Designer’s Guide
1070
3-3
Table 3-1. Interface Memory Bit Definitions
Mnemonic
Location
Default
Name/Description
12TH
08:4
0
Select 12th Order. When control bit 12TH is a 1, the tone detectors operate as one 12th order filter (uses
FR3).When 12TH is a 0, the tone detectors operate as three parallel independent 4th order filters (FR1,
FR2, FR3).The 12th bit is valid in all reception modes except speakerphone and V.23.
ABIDL
09:3
–
Abort/Idle. In HDLC mode, when the modem is configured as a transmitter and control/status bit ABIDL is a
1, the modem will finish sending the current DBUFF byte. The modem will then send continuous ones if
ZEROC is a 0, or continuous zeros if ZEROC is a 1. When ABIDL is a 0, the modem will not send
continuous ones or zeros. If ABIDL is reset one DCLK cycle after being set, the modem will transmit eight
continuous ones if ZEROC is a 0, or eight continuous zeros if ZEROC is a 1. ABIDL is also set by the
modem when the underrun condition occurs (bit OVRUN is a 1) and the modem will send at least eight
continuous ones (if ZEROC is a 0) or eight continuous zeros (if ZEROC is a 1).To stop continuous ones or
zeros transmission, ABIDL must be reset by the host.
In HDLC mode, when the modem is configured as a receiver and status bit ABIDL is a 1, the modem has
received a minimum of seven consecutive ones. To recognize further occurrences of this abort condition,
ABIDL must be reset by the host.
ACC1
05:7
1
RAM Access 1. When control bit ACC1 is a 1, the modem accesses the RAM associated with the address
in ADD1, and the AREX1 and CR1 bits. WRT1 determines if a read or write is performed.
ACC2
15:7
0
RAM Access 2. When control bit ACC2 is a 1, the modem accesses the RAM associated with the address
in ADD2, and the AREX2 and CR2 bits. WRT2 determines if a read or write is performed.
ADD1
04:0-7
17
RAM Address 1. ADD1, in conjunction with AREX1, contains the RAM address used to access the
modem's X and Y Data RAM (CR1 = 0) or X and Y Coefficient RAM (CR1 = 1) via the X RAM Data 1 least
significant byte (LSB) and most significant byte (MSB) words (02:0-7 and 03:0-7, respectively) and the Y
RAM Data 1 LSB and MSB words (00:0-7 and 01:0-7, respectively).
ADD2
14:0-7
00
RAM Address 2. ADD2, in conjunction with AREX2, contains the RAM address used to access the
modem's X and Y Data RAM (CR2 = 0) or X and Y Coefficient RAM (CR2 = 1) via the X RAM Data 2 LSB
and MSB words (12:0-7 and 13:0-7, respectively) and the Y RAM Data 2 LSB and MSB words (10:0-7 and
11:0-7, respectively).
AEOF
15:5
0
Automatic End of Frame. When the modem is configured as an HDLC transmitter and AEOF control bit is
a 1, the modem interprets an underrun condition as an end of frame and outputs the FCS and at least one
ending flag. (HDLC mode.)
AGCDIS
1A:2
0
AGC Disable. In Voice Codec Mode (CONF = 90h or 98h) or Audio Codec Mode (CONF = 92h or 94h), the
AGCDIS control bit disables (AGCDIS = 1) or enables (AGCDIS = 0) AGC in the voice/audio coder.
AGCIE
0F:4
1
AGC in IIA ADC Enable. In speakerphone mode, the AGC in the IIA ADC is enabled when control bit
AGCIE is a 1; the AGC gain is forced to 0 dB when AGCIE is a 0.
AGCSEL
14:6
0
AGC Select. When control bit AGCSEL is a 0, the voice/audio coder Energy AGC is selected. When
AGCSEL is a 1, the voice coder Classifier AGC is selected. (Voice Codec Mode and Audio Codec Mode)
AGCXE
0F:3
1
AGC in XIA ADC Enable. In speakerphone mode, the AGC in the XIA ADC is enabled when control bit
AGCXE is a 1; the AGC gain is forced to 0 dB when AGCXE is a 0.
ANDOR
0A:5
0
AND/OR Bit Mask Function. When control bit ANDOR is a 1 and the programmable interrupt is enabled
(PIE bit = 1), the modem will assert ~IRQ1 if all the bits in the register specified by ITADRS and masked by
ITBMSK trigger the interrupt and control bit PIREQ has been previously reset by the host. When ANDOR is
a 0 and the programmable interrupt is enabled, the modem will assert ~IRQ1 if any one of the bits in the
register specified by ITADRS and masked by ITBMSK trigger the interrupt and control bit PIREQ has been
previously reset by the host.
ANS
15:2
0
Answer. When configuration bit ANS is set, the modem is in answer mode; when reset, the modem is in
originate mode. If the modem is in Answer Mode (ANS= 1), then the transmit data rate is 1200 bps, and the
receive data rate is 75 bps. If the modem is in Originate mode, the transmit data rate is normally 75 bps, and
the receive data rate is 1200 bps. (V.23)
When V.23 Half Duplex mode is selected (V23HDX = 1), ANS should be set to 0 to configure 1200 bps
transmit and receive data rates.
Since this is a configuration bit, the SETUP bit (1F:0) must be set after any change in the ANS bit.
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