*Notice: The information in this document is subject to change without notice
Tsi301
Notes
Tsi301 HyperTransport to PCI User Manual
3-20
•
Memory Mapped Cycles.
The HyperTransport PCI bridge implements a 40-bit space for memory
mapped accesses and decodes DAC accesses for addresses above 4 GB. In
Pass1
, address bits
above bit 39 are ignored and result in the 40-bit space aliasing through PCI’s 64-bit memory mapped
space. In
Pass2
, any address with a non-zero value in the top 24 bits of the 64 bit PCI address is left
on the PCI bus.
Memory mapped addresses are compared to the range defined by the Memory Range Base Addr and
Memory Range Limit Addr CSRs; and the range defined by the Prefetchable Memory Range Base Upper and
Prefetchable Memory Range Base Addr, and Prefetchable Memory Range Limit Upper and Prefetchable
Memory Range Limit Addr CSRs. If the VgaEn bit in the Bridge Control CSR is set, the address is also
compared to the fixed range of 00_000A_0000h – 00_000B_FFFFh. Addresses that don’t fall into any of these
ranges are accepted for forwarding to HyperTransport, as long as the MasterEn bit in the Command CSR is
set and bits [39:32] <= Fch.
•
I/O Cycles.
The HyperTransport PCI bridge implements a 25-bit space for I/O accesses. In
Pass1
,
address bits above bit 24 are ignored and result in the 25-bit space aliasing through PCI’s 32 bit I/O
space. In
Pass2
, the top 7 of the 32 bits must be 0 for the access to reach HyperTransport.
I/O addresses are compared to the range defined by I/O Range Base Upper and I/O Base, and I/O Range
Limit Upper and I/O Limit CSRs. If the IsaEn bit in the Bridge Control CSR is set, a series of holes are created
in this range at the top 768 bytes of each 1 KB block in the low 64 KB. If the VgaEn bit in the Bridge Control
CSR is set, I/O addresses in the low 64 KB have their bottom 10 bits compared to the ranges 3B0h – 3BBh
and 3C0h – 3DFh. Accesses that miss all the enabled ranges are accepted for forwarding to HyperTransport,
as long as the MasterEn bit in the Command CSR is set.
•
Configuration and Special Cycles.
The HyperTransport PCI bridge never acts as a target for
configuration or special cycles on the PCI bus.
3.6.2 PCI Posted Write Queue
The HyperTransport PCI bridge responds as a PCI write target to PCI Memory Write, Memory Write Invali-
date, and I/O Write commands. All of these writes are posted to the HyperTransport chain. The HyperTrans-
port PCI bridge never responds to Configuration Writes. A total of 192 bytes of buffering for posted write data
is provided.
Memory Write and Memory Write Invalidate commands stream data into the chip, disconnecting either on
4-KB boundaries or when all of the internal buffer space is filled. The HyperTransport PCI bridge generates
the largest HyperTransport write operations possible, issuing them continuously as the data for each write is
received from PCI.
As the bandwidth of HyperTransport exceeds the bandwidth of PCI, it is expected that the internal buffers
will not fill and memory writes will proceed continuously at the full bandwidth of the PCI bus.
I/O writes are not allowed to stream and always disconnect after a single data beat on the PCI bus (32
bits). Each I/O write is issued to HyperTransport as an independent request.
3.6.3 PCI Delayed Request Buffers
The HyperTransport PCI bridge acts as a PCI read target for PCI Memory Read, Memory Read Line,
Memory Read Multiple, and I/O Read commands. The HyperTransport PCI bridge never responds to configu-
ration read or interrupt acknowledge accesses. All supported read transactions are implemented as PCI
delayed reads.
Incoming reads are assigned to a delayed request buffer. There are four delayed request buffers, enabled
under CSR control, allowing up to four PCI read requests to be in progress at one time. If no delayed request
buffers are free, the incoming request is retried until one is available. Once the request is assigned to a buffer,
the interface continues to retry it on the PCI bus while read requests are issued to the HyperTransport inter-
face.
3.6.4 Prefetching
The HyperTransport PCI bridge supports a variety of prefetching options configured under CSR control
using the Read Control CSR (62h:60h), however:
