*Notice: The information in this document is subject to change without notice
Tsi301
Notes
Tsi301 HyperTransport to PCI User Manual
3-20
The PCI interface can be enabled to perform fast back-to-back transactions. When the bus is configured
as 64 bit at reset (PCI_AD[14]), the interface automatically asserts P_REQ64_N on all transactions for which
it is legal. When the bus is configured as 32 bit, the interface automatically shuts down both its input and
output buffers for P_AD[63:32], P_CBE_N[7:4], P_REQ64_N, P_ACK64_N, and P_PAR64.
The PCI interface supports Type 0 PCI configuration cycles to device numbers 0 through 15. P_AD[31:16]
are driven with a one-hot encoding during these configuration cycles, with bit 16 asserted for accesses to
device number 0. This logic assumes that one P_AD bit is connected to the IdSel# pin on each PCI slot
through a series resistor on the board. If the resistor increases the settling time of IdSel# to the point at which
it doesn’t make timing in one PCI cycle, the IdSelCharge field of the PCI Control register may be set to a
nonzero value to provide more time. Setting the IdSelCharge field of the PCI Control register to a nonzero
value opens a window where the HyperTransport PCI bridge may lose control of the PCI bus because of its
failure to drive P_FRAME_N immediately, which may have implications about forward progress.
If a request is retried or disconnected on the PCI bus, that fact is reported back to the ORC. The controller
finishes any data movement associated with the disconnected transaction and then reissues the request from
the point of disconnection. It continues to reissue a request until it completes or until the retry timer for the
request expires. Because the ORC can handle multiple outstanding requests, transactions repeatedly retried
or disconnected may be reordered or interleaved.
3.5.3 PCI Response Data Buffer
The PCI response data buffer contains read data returned from outbound reads to either the PCI interface
or the CSR master. This data buffer is a RAM holding 48 DW of data, 16 DW each for three HyperTransport
read requests.
Because multiple reads may be in progress to the PCI and CSR interfaces at one time, with their returning
data getting interleaved by PCI disconnects, this cannot be a FIFO structure. Each buffer accumulates data
for its request until all requested DW are returned. This data is then combined with response header informa-
tion from the ORC to form the response packet for the operation.
Once the response is issued, the buffer is retired. Nonposted write requests still occupy space in the
response data buffer, even though they have no read data.
3.5.4 End of Interrupt
When an interrupt is configured as level sensitive, upstream interrupt logic must respond to an interrupt
request packet with an end of interrupt (EOI) packet. Until the EOI packet is received by the HyperTransport
PCI bridge, no new interrupt request packets will be generated by that interrupt pin.
Note:
See Interrupt Generation, Section 3.6.12.
3.6 Inbound Transactions
Inbound transactions are requests from the PCI bus or interrupt controller across HyperTransport to the
host bridge. From there, they are routed to destinations behind the host bridge or reflected peer-to-peer back
onto the HyperTransport chain. If the request is nonposted, the transaction also includes the response from
the host bridge back to the original requesting unit.
The HyperTransport PCI bridge operates as a PCI target for requests from external PCI devices. All
accepted requests are forwarded to the HyperTransport link interface leading to the host. Reads go though
the delayed request buffers and are handled on the PCI bus as delayed requests. All writes, regardless of
type, are posted into the posted request queue and allowed to immediately complete on the PCI bus.
3.6.1 PCI Address Map
Accesses on the PCI bus are checked against the following ranges to determine whether the HyperTrans-
port PCI bridge is the target of the access and should assert P_DEVSEL_N to accept the request. The Hyper-
Transport PCI bridge makes this determination with medium DEVSEL# timing. When configured as a 64-bit
target at power up, the HyperTransport PCI bridge asserts P_ACK64_N in response to P_REQ64_N for
requests it accepts.
