*Notice: The information in this document is subject to change without notice
Tsi301
Notes
Tsi301 HyperTransport to PCI User Manual
3-20
3.6.9 Transaction Disconnects
Read transactions may be disconnected by the bridge when required data is not available in time, or by the
master. The Delayed Request buffer remains in use until all outstanding HyperTransport prefetch requests
receive their responses; then it is retired and any leftover data discarded. Each delayed request buffer also
has an associated discard timer loaded with one of two values determined by the Secondary Discard Timer bit
(9) of the Bridge Control CSR (3Eh) when the data is received from HyperTransport. If this timer expires
before the data is called for by the PCI master, the data is discarded and the buffer retired.
3.6.10 Performance Variables
The following PCI inbound read performance characteristics can be tuned for best performance in a given
system architecture or traffic load by using fields in the Read Control CSR. Independent prefetch controls are
also provided for both MemRdMult and MemRdLine commands. If prefetching is enabled for MemRd
commands, the MemRdLine values are used.
•
PCI Delayed Request.
The PCI Delayed Request field controls the number of PCI requests that can
be fetching data at one time. Having multiple delayed requests generally reduces average latency on
the PCI bus by fetching for multiple PCI requests simultaneously. However, setting the number of
fetches too high may interfere with continuous prefetching.
•
When the number of fetches is set too high, a large number of reads may be sent to HyperTransport
due to other PCI reads between the initial fetches and the ones generated as the data buffers drain to
PCI. If these subsequent fetches backup far enough, they may not succeed in returning data in time to
keep the burst from ending on the PCI bus at which point their data might be discarded.
•
Ideal Prefetch Count.
If the available HyperTransport bandwidth exceeds the PCI bandwidth, there is
an ideal prefetch count for large transfers. The ideal prefetch count is determined by dividing the
number of bytes that can be transferred on the PCI bus in the round-trip read latency by 64 (the
number of bytes in a prefetch request).
•
The number of bytes that can be transferred on the PCI bus depends on the bus characteristics: 32 or
64 bit, 33 or 66 MHz, or 25 or 50 MHz.
•
Round-trip read latency depends on the latency of and distance to the target.
•
With continuous prefetching enabled, the HyperTransport PCI bridge will be able to keep up with an
arbitrary length burst.
•
InitCount.
If the available HyperTransport bandwidth is less than the PCI bandwidth, there is no ideal
prefetch count. HyperTransport will eventually be forced to disconnnect on a long burst because it will
be out of data. Disconnects like this waste PCI bandwidth and waste HyperTransport bandwidth by
discarding the prefetched data.
•
In this case, setting the InitCount above zero will require more data to be on hand before the
transaction is allowed to reconnect on PCI. The nonzero setting increases utilization of
HyperTransport bandwidth at some cost in PCI latency, but reduces the number of wasteful
disconnects. Continuous prefetching should also be disabled since the extra prefetches would
probably not arrive in time to be used and would likely be discarded.
3.6.11 Outbound Data Buffer
•
The HyperTransport PCI bridge contains a central data buffer (sixteen 64-byte entries) for the
accumulation of read response data to return to the PCI bus. Entries in the buffer are assigned to PCI
reads by the same algorithm used to assign srcTags—the bottom four bits of the srcTag are the entry
number. Because of this one-to-one correspondence, no separate mechanism for allocation of data
buffers is required. Data from returning HyperTransport responses is loaded into the buffer based on
the srcTag in the response header and drained out to the PCI bus when the delayed request
reconnects.
3.6.12 Interrupt Generation
The HyperTransport PCI bridge interrupt controller consists of four blocks of generic interrupts, four inter-
rupts per block, and one set of special interrupts. In
Pass2
, the special interrupts are not available.
