*Notice: The information in this document is subject to change without notice
Tsi301
Notes
Tsi301 HyperTransport to PCI User Manual
4-6
4.3.2 Outbound Operations
Latency from the header presented at the HyperTransport transmit interface through the packet generator
to the Tx Sync FIFO = 2 * Core Clock
Minimum latency through the Tx Sync FIFO = 1 * Core Clock. Actual latency depends on SIP settings for
the Tx Sync FIFO.
Latency through the HyperTransport PHY from the doubleword available at the output of the Tx Sync FIFO
to the first byte of the packet on the link = 1.75 * LDT Tx Clock
4.3.3 Latency Through the HyperTransport PCI Bridge
Reference clock periods for the HyperTransport PCI bridge are:
•
LDT Rx Clock at 400 MHz = 2.5 ns
•
LDT Tx Clock at 400 MHz = 2.5 ns
•
Core Clock at 133 MHz = 7.5 ns
•
PCI Clock at 66 MHz = 15 ns
Forwarding Path Idle Latency
The formula for calculating the minimum forward path idle latency through the HyperTransport PCI bridge
is
HyperTransport Rx PHY delay + Rx Sync FIFO delay + HyperTransport Link I/F delay + logic
delay(forwarding) + HyperTransport Link I/F delay + Tx Sync FIFO delay + HyperTransport Tx PHY delay
The calculation is
(3 * LDT Rx Clock) + (2 * Core Clock) + (2 * Core Clock) + (0 * Core Clock) + (2 * Core Clock) + (1* Core
Clock) + (1 * LDT Tx Clock)
= (3 * 2.5) + (7 * 7.5) + (1.75 *2.5)
= 7.5 + 52.5 + 4.4 = 64.4 ns
Data Alignment Factor (maximum) =
(1 * Core Clock) + (2 * LDT Rx Clock) = 11.5 ns
Clock Alignment Factor (maximim) =
(2 * Core Clock) + (1 * LDT Rx Clock) = 17 ns
Extraction Path Idle Latency
The formula for calculating the minimum extraction path idle latency through the HyperTransport PCI
bridge is
HyperTransport Rx PHY delay + Rx Sync FIFO delay + HyperTransport PCI Link I/F delay + logic delay
(extraction to PCI) + PCI I/F delay
The calculation is
(3 * LDT Rx Clock) + (2 * Core CLock) + (2 * Core Clock) + (3 * Core Clock) + (4 * PCI Clock)
= (3 * 2.5) + (7 * 7.5) + (4 * 15)
= 7.5 + 52.5 + 60 = 124 ns
Data Alignment Factor (maximum) =
(1 * Core Clock) + (2 * LDT Rx Clock) = 12.5 ns
Clock Alignment Factor (maximim) =
(2 * Core Clock) + (1 * LDT Rx Clock) = 17.5 ns
