*Notice: The information in this document is subject to change without notice
4-6
Notes
Chapter 4 Clock and Timing Relationships
The HyperTransport PCI bridge has only one PLL. The PCI clock (REFCLK_H/L input) is 1/4 of the core
clock or 1/2 of the core clock. See Table 4.1 for core clock frequencies.
4.1 Clock Dividers
The PLL has three dividers for generating divided VCO clocks. The divider selects come from the P_AD
bus during reset as follows:
•
Link0 Clock Divider Select
– L0_clkSel P_AD[29:27]
•
Link1 Clock Divider Select
– L1_clkSel P_AD[26:24]
•
Core Clock Divider Select
– coreClkSel P_AD[23:22]
Note:
The frequencies given in Table 4-1 are the HyperTransport frequency per wire. The actual
HyperTransport data rate is 2 times the rate of this frequency.
4.2 Clock Features
4.2.1 Definitions
coreClk
MHz
Lx_TX_CLK_H/L
MHz
REFCLK_H/L
MHz
coreClkSel Lx_clkSel P_M66EN
100
200
25
01
001
0
100
200
50
01
001
1
100
400
25
01
000
0
100
400
50
01
000
1
133
200
33
00
001
0
133
200
66
00
001
1
133
400
33
00
000
0
133
400
66
00
000
1
Table 4.1 Clock Settings
Clock
Description
Max Speed
Pin
L0_RxWlnkClk
Link0, 1/2 LDT Rx Clock (internal)
200 MHz
TCK
L0_TxWlnkClk
Link0, 1/2 LDT Tx Clock (internal)
200 MHz
TCK
L1_RxWlnkClk
Link1, 1/2 LDT Rx Clock (internal)
200 MHz
TCK
L1_TxWlnkClk
Link1, 1/2 LDT Tx Clock (Internal)
200 MHz
TCK
ref33Clk
Non-PLL 33MHz Ref (internal)
33 MHz
REFCLK_H
clk
Core Clk (internal)
133 MHz
REFCLK_H
Table 4.2 HyperTransport PCI Bridge Internal Clocks
