3028 Turbo Statistical Multiplexer
I-2
154001UA
SDLC/HDLC
SDLC/HDLC
SDLC/HDLC
SDLC/HDLC
SDLC/HDLC
OVERVIEW
OVERVIEW
OVERVIEW
OVERVIEW
OVERVIEW
SDLC/HDLC refers to the bit-oriented synchronous data link control protocols
that are based on HDLC. The basic format for SDLC/HDLC is a frame (Figure I-1)
The beginning and ending flags each consist of an 8-bit binary pattern of 01111110
(7E hex). These fields serve as reference points for the position of the address and
control fields and initiate transmission error checking. The ending flag may serve
as the beginning flag for the next frame. Multiple flags may be repeated between
frames to keep the line in an active state. The idle state of the line may be flags or
all 1's (MARK). While the channel is idling MARK, any data input from the
channel which is not a flag character is discarded.
SDLC/HDLC is code transparent and the only unique bit stream is the flag field.
The logic will not allow the 01111110 pattern to be transmitted in other parts of the
frame. The transmitter watches the transmit data stream and automatically inserts
a 0 after any successive five 1's. The receiver searches the receive data stream for
five consecutive 1's and deletes the next bit if it is a 0.
2 031 I-1
Flag Address Control User
Data
FCS
Flag
Figure I-1. SDLC/HDLC Frame Format
Note
In order for SDLC/HDLC to function, both the remote and
local multiplexers must be 3028 Turbo, CTS 2031, CTS
2031 Turbo, CTS 2530 or Paradyne 2030 multiplexers
with SDLC/HDLC features. (This enhancement is NOT
compatible with DCX SLINK.) It can be used in a DCX
network as long as the two ends are 3028 Turbo's, CTS
2031's or Paradyne 2030's; however, multimode connec-
tions will add delays that may cause time-outs.