60
Timing Diagram
Pulse output changes in reference to the input status of each signal as
illustrated below.
Shared Memory Setting
Counter setting
Setting the operation mode for each counter CH.
In this example, counter functions is used in direction control mode,
output pulses are counted via internal connection, and
「
FFFFFF02
」
is
recorded in shared memory address 100h and 101h.
Shared memory 100h, 101h settings
· · ·
· · ·
PLS0 Enable signal
(R4.0, R3.8)
Output of forward pulse
PLS0 Start signal
(R4.1, R3.12)
PLS0 Direction
signal (R4.2, R2.0)
PLS0 A Pulse
output (R2.8)
PLS0 B Direction
control signal (R2.9)
Output of reverse pulse
Pulse output starts when edge rise of Start signal is
detected while Enable signal is ON.
R0.7
R0.6
R0.5
R0.4
R0.3
R0.2
R0.1
R0.0
CH3
CH2
CH1
CH0
Input
mode
Functions
etting
Input
mode
Functions
etting
Input
mode
Functions
setting
Input
mode
Functions
setting
F
F
F
F
F
F
0
2
Unused
Unused
Unused
Unused
Unused
Unused
Direction
control
Internal
connection
External input
Setting item
(bit) 32
Counter
number
Set value
Settings
16 15
0