58
Shared Memory Setting
PLS/PWM setting
Pulse output form is determined by PLS/PWM setting.
In this example, enter
「
FFFFFFF8
」
into shared memory addresses
140h and 141h, because in data refreshing direction control mode,
pulse output starts from R2.8 and R2.9 (PLS0) when PLSx Start signal
edge rises or data is refreshing.
Shared memory 140h, 141h settings
PLS/PWM frequency setting
This setting determines the frequency of PLS/PWM pulses.
In this example, enter
「
K10000
」
(H2710) into shared memory
addresses 148h and 149h, because pulse output starts at R2.8 and R2.9
(PLS0) at 10 kHz.
At the moment when speed change input turns ON at R0.3, re-enter
「
K20000 (H4E20)
」
.
Shared memory 148h, 149h settings
Shared memory 148h, 149h settings (R0.3 ON)
Unused
Unused
Unused
Unused
PLS3
PLS2
PLS1
PLS0
Unused
Unused
Unused
Unused
Form
setting
Form
setting
Form
setting
Form setting
F
F
F
F
F
F
F
8
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Refresh by Start
signal or data change
(Direction control)
Output number
(bit) 32
Setting item
Set value
Settings
16 15
0
PLS0/PWM0 frequency setting
0
0
0
0
2
7
1
0
K 10000
Setting item
(bit) 32
Set value
16 15
0
Settings
PLS0/PWM0 frequency setting
0
0
0
0
4
E
2
0
K 20000
Setting item
(bit) 32
Set value
16 15
0
Settings