53
Step 2. Shared memory setting (PLS/PWM frequency setting)
●
Configure frequency of output pulses after PLS/PWM setting of
shared memory.
●
Frequency is set within the range of 1 Hz to 100 kHz by 1 Hz unit.
Output turns OFF (pulse stop) when frequency setting exceeds
131.072 kHz.
●
When frequency is set to 0 Hz and data is refreshed, pulse output is
stopped.
Make sure to access shared memory by 2 word unit.
ATTENTION
See
"PLS/PWM Flag" in Appendix B
for shared memory addresses.
NOTE
PLS: K1 to K100000
PLS: K1 to K100000
PLS: K1 to K100000
PLS: K1 to K100000
Address: 148h 149h
Address: 14Ah, 14Bh
Address: 14Ch 14Dh
Address: 14Eh 14Fh
PLS 0/PWM 0
frequency setting
PLS 1/PWM 1
frequency setting
PLS 2/PWM 2
frequency setting
PLS 3/PWM 3
frequency setting
• Make sure to access shared memory by 2 word unit.
• On shared memory, PLS/PWM frequency setting should
be located after PLS/PWM setting.
If not, it may not work properly.
• Do not set a value out of the permitted range. It may cause
errors.
• Error detection upper limit of the unit is 1048.575 kHz.
(1048.575 kHz = FFFFFh)
When setting exceeds the limit, the value based on
the lower 20-bit is applied.
ATTENTION
•
PLS/PWM flag is prepared at shared memory addresses 142h and 143h. Pulse
output can be monitored by reading the flag in these addresses. See
“PLS/PWM
Flag” in Appendix B
for details.
•
See
"Shared Memory Areas" in Appendix A
for shared memory addresses.
NOTE