66
Shared memory 120h, 121h settings (Stop pointer)
PLS/PWM Setting
Pulse output form is determined by PLS/PWM setting.
In this example, enter
「
FFFFFFF6
」
into shared memory addresses
140h and 141h, because in frequency (speed) changing direction
control mode, pulse output starts from R2.8 and R2.9 (PLS0) when
PLSx Start signal edge rises, or in comparison output mode.
Shared memory 140h, 141h settings
PLS/PWM frequency setting
This setting determines the frequency of PLS/PWM pulses.
In this example, enter
「
K300 (H12C)
」
into shared memory addresses
148h and 149h, because pulse output starts at R2.8 and R2.9 (PLS0) at
10 kHz The entered value is replaced with
「
K1000 (H3E8)
」
before
comparison coincidence (CMP0) turns ON, to prepare for pulse
frequency (speed) change in comparison output mode. It changes
again to
「
K300 (H12C)
」
before deceleration, and
「
K0 (H0)
」
before
stop.
Shared memory 148h, 149h settings (Acceleration, deceleration)
Shared memory 148h, 149h settings (At Max. speed)
Shared memory 148h, 149h settings (Stopped)
Comparison output set value (CMP0)
0
0
0
0
2
7
1
0
K 10000
Setting item
(bit) 32
Set value
16 15
0
Settings
Unused
Unused
Unused
Unused
PLS3
PLS2
PLS1
PLS0
Unused
Unused
Unused
Unused
Form
setting
Form
setting
Form
setting
Form setting
F
F
F
F
F
F
F
6
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Data refresh with
Start signal or
comparison output
Output number
(bit) 32
Setting item
Set value
Settings
16 15
0
PLS0/PWM0 frequency setting
0
0
0
0
0
1
2
C
K 300
Setting item
(bit) 32
Set value
16 15
0
Settings
PLS0/PWM0 frequency setting
0
0
0
0
0
3
E
8
K 1000
Setting item
(bit) 32
Set value
16 15
0
Settings
PLS0/PWM0 frequency setting
0
0
0
0
0
0
0
0
K 0
Setting item
(bit) 32
Set value
16 15
0
Settings