56
Shared Memory Setting
PLS/PWM setting
Setting the Pulse output mode for PLS/PWM setting.
In this example, enter
「
FFFFFFF8
」
into shared memory addresses
140h and 141h, because in data refreshing direction control mode,
pulse output starts from R2.8 and R2.9 (PLS0) when PLSx Start signal
edge rises or data is refreshing.
Shared memory 140h, 141h settings
PLS/PWM frequency setting
This setting determines the frequency of PLS/PWM pulses. In this
example, enter
「
K10000 (H2710)
」
into shared memory addresses
148h and 149h, because pulse is sent out from R2.8 and R2.9 (PLS0) at
10 kHz.
Shared memory 148h, 149h settings
Unused
Unused
Unused
Unused
PLS3
PLS2
PLS1
PLS0
Unused
Unused
Unused
Unused
Form
setting
Form
setting
Form
setting
Form setting
F
F
F
F
F
F
F
4
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Data refresh with
Start signal
(Direction control)
Output number
(bit) 32
Setting item
Set value
Settings
16 15
0
PLS0/PWM0 frequency setting
0
0
0
0
2
7
1
0
K 10000
Setting item
(bit) 32
Set value
16 15
0
Settings